Another of the EDA industry's more talked-about secrets came to the surface this morning, as Infinisim announced its analog simulation product. Aimed squarely at the problem of performance and capacity in existing SPICE-accurate simulators, the new tool is in a way the culmination of the work of several major players in the simulation space.

The technology experts behind Infinisim include Zakir Hussain Syed, CTO; Perry Gee, VP Engineering; and Dileep Devekar, VP or R/D. The former two are early players at Simplex Solutions, and Divekar has written a book on FET modeling.

The secret sauce in Infinisim's Real-Time Adaptive Simulation product—RASER originates in PhD work done by Syed. "There are really no new model-evaluation or solver technologies here," Syed explained. "The performance gains in RASER come from the adaptive part: subdividing the problem at each time step and choosing the optimum algorithms to use in each portion of the design at that step."

There is little need to dwell on the need for greater speed in analog simulation. "A not-that-complicated PLL can take a month of simulation time in SPICE," Syed said. Clearly, as analog circuits become merged analog-digital circuits, as they encounter process variations, and as they become sensitive to issues such as supply noise, designers need a tool that can deal with blocks that may have huge numbers of transistors, but without compromising on accuracy.

Syed contrasted RASER to FastSPICE or similar approaches that achieve speed by making simplifying assumptions. RASER runs a full SPICE simulation, using Infinisim-optimized versions of known model-analyzers and matrix solvers. It achieves speed by at each step adapting to the mathematical problem if faces.

On every time step, Syed explained, RASER's adaptive control algorithm examines key parameters for each node in the design: charge, current, and di/dt, for instance. From this data, the algorithm organizes the nodes into blocks best suited for a particular set of analysis and solver algorithms. To give some trivial examples, if a group of nodes in the digital section of a design is quiescent, RASER may simply skip the whole group for this step. If a group of nodes lends itself to a faster model analysis because of its current state, RASER may group those nodes together and deal with them more quickly with a specialized model-analyzer. If a group of nodes will produce a particular sparse-matrix situation allowing for a high-speed solver to be used, the program will recognize that opportunity as well.

The result is that RASER does full SPICE simulation at full resolution on the full circuit, but it doesn't waste time using the same analysis and solver algorithms over and over on every node, every step. The savings depend on the structure and level of activity in the circuit, but they can be dramatic, Syed said. The company is claiming typical speed-up of 50 times on transient analysis applications compared to conventional SPICE. For some particular circuits such as memory arrays, in which there is a great deal of quiescence, the program can be literally thousands of times faster than conventional SPICE, Syed said. "Typically digital nets have very high latency, so you can save a lot of work by exploiting that," he explained.

"This makes possible full-chip simulation of analog chips with heavy digital intervention, really for the first time," said Samia Rashid, president of the new company. "We are offering the speed and capacity to handle an entire chip, and we guarantee SPICE accuracy." The guarantee part could be a little hard to collect on in practice, since for many of the designs on which RASER is claimed to shine, conventional SPICE tools never converge at all. Designers can only assess the tool's accuracy by comparing to silicon.

RASER may be just in time for design teams dealing with the heavy digital content in precision analog blocks at 65 nm and below. But even this approach has challenges ahead. One of these is signal integrity. As designers include leakage, parasitic-coupling, and substrate-coupling paths in their analyses to capture noise issues, models and netlists tend to explode, and simulation times go through the roof. RASER may prove ideal for that. But the presence of low-level but high-frequency noise challenges RASER's approach by reducing the number of quiescent nodes in the circuit on any given step. "We have spent a lot of time talking to design teams about substrate noise in particular," Syed said, "and we have a prototype that uses a specialized solver to deal with it."