Hi folk, I’ve been in hunkered down mode for the last few weeks researching and writing my next cover story. This one’s on IC reliability. It’s a subject I haven’t tackled before and quite frankly is a subject I haven’t seen too much coverage about, even the EE trade books.

I actually learned a quite a bit of information about how design groups and more so semiconductor companies and IC manufactures look at reliability throughout product development. It’s actually a story that could have been a small novella. In print, space is always a bit limited so the print version of the story will cover the more traditional failure mechanisms designers and manufacturers need to watch out for. Some of those failure mechanisms pop up one process generation then are handled quickly by the semi guys. Some failure mechanisms are starting to rear their ugly heads again and are affecting new types of circuits (I’m being vague on purpose).

The full version of the article, which I hope will run its entirety online, actually goes into how reliability may become even more tricky as we move into new process nodes and have to deal with issues such as increasing transistor leakage, process variation and the like.

I interviewed the folks at nVidia, IBM, Texas Instruments, Xilinx, Cadence, Magma, Synopsys and Apache. Unfortunately I wasn’t able to get everyone’s input into the story but they all helped with my education on the subject, so thanks to those folks (and if you don’t see your names let alone quotes in the story, don’t be mad).

We’ve all heard of design for manufacturing, so I was wondering if in the consumer IC design space, if it’s also time for design for reliability? The answer to that is that IC reliability is seemingly something the semiconductor guys have in hand but the playing field is shifting as new process geometries present new challenges. I hope you enjoy the article when it comes out in early March.

So now that I have that one in the bag (I hope), I’m headed to DesignCon 2008 next week and I’ll be covering various panels and sitting in on sessions (not meeting with vendors, pr folks, cause I want to hear the live activities: panels, keynotes, drunk execs at the bar…etc… Catch me any other time for face to face meetings).

I’m also moderating DesignCon 2008’s annual DFM panel on Wednesday February 6 from 2:00pm to 3:30pm. This year’s panel is called “Where is the ROI in DFM?” This aught to be very interesting and it has a great group of panelists. Instead of sitting through PowerPoint presentations for each panelist, we’re going to do my favorite panel format in which we jump into audience Q&A from the very start. So if you have any pressing questions related to the DFM biz for the folks at AMD, Cadence, Freescale, Toppan Photomasks or TSMC feel free to join us. Hope to see you there.