Reducing simulation debugging time, the compiled-code Verilogger Extreme Verilog 2001 simulator provides fast simulation of RTL and gate-level simulations using SDF (Synopsys Delay Format) timing information. Verilogger Extreme claims eight-times-faster RTL simulation and 30-times-faster gate-level simulation than VeriLogger Pro. The simulator supports design libraries and design flows for all major ASIC and FPGA vendors and comes bundled with the vendor’s BugHunter Pro graphical Verilog/VHDL integrated development environment. Suiting low-memory usage, the product allows large designs to run on memory-constrained laptops. VeriLogger Extreme is available on Linux, Solaris, and Windows; a perpetual license costs $4000 on Windows, with a 24% discount through March 2007. Current Verilogger Pro customers with maintenance contracts can upgrade for free.

SynaptiCAD, www.syncad.com