Monday, October 15, 2007

Design-test connection bolstered by Magma’s move


In another move toward bringing design and test closer together, Magma Design Automation announced today that it is working with Inovys and Source III to smooth a path from the EDA tool provider’s Talus automatic test pattern generation (ATPG) tools to the tester providers’ hardware-based tester equipment and test programs, respectively.

Magma’s Kam Kittrell, general manager of the company’s design implementation business unit said that Magma recognizes that test is more than patterns generated by EDA tools and as a result, the company is broadening its product portfolio to better address the design and test challenges of nanometer ICs. “We are also committed to partnering with other test technology leaders. Delivering interoperability with leading test providers' products is a significant milestone in Magma's DFT product roadmap and ensures that our products work with our mutual customers' test equipment.”

The design and test communities have long recognized that huge benefits can be add by bringing the two disciplines closer together. Mentor Graphics Corp. has been working with Advantest for a number of years and also confirmed that it has relationships with all major hardware test provider including Teradyne and Verigy, as well as with Inovys and Teseda. 

In 2004, Agilent Technologies linked its test equipment with Synopsys Inc.'s ATPG software in a move the companies hoped would speed fault finding in ICs

Then, last December, Cadence Design Systems Inc. also announced a partnership with Advantest meant to improve time-to-market and allow more complete testing of complex digital devices for automobiles through a methodology for zero-defect testing of digital automotive electronics.

Software test supplier LogicVision’s present and CEO Jim Healy noted in an Electronic Business article last year that in an era when semiconductor costs are outpacing market growth, there's no doubt that the industry would like to see faster automatic test equipment (ATE) development that carries a low price tag and a big roadblock to achieving this is the "wall" between design and test, along with semiconductors becoming increasingly complex, which is keeping test costs high.

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In the article, Healy explained that one possible way to reduce costs may be right under the industry's nose, but that organizational dynamics are preventing it from being implemented. Technology and methodologies exist to trim the cost of test by at least 50 percent—simply by integrating ATE with supporting design for test (DFT) to help provide real-time, at-speed, built-in test capabilities at probe and final test, he explains.

Today’s move by Magma seems definitely a step in the right direction. Maybe we will see other ATE players such as National Instruments, Credence and Teradyne make similar agreements to bring down the wall between DFT and ATE.



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