Is FPGA a simpler puzzle for ASIC designers? By Michael Santarini, Senior Editor
With rising mask costs, complexity, and tool expenses to develop ASICs and SOCs, many design groups today are opting to implement their production designs in FPGAs. But, before designers make the leap, there are several factors—good and bad—they should consider.
Design Features
Interface chips: Between logic and a hard place By Paul Rako, Technical Editor
Interface chips must mediate between ever-lower logic voltages and real-world loads. Here are the circuits and techniques you need to know.
Autovectorization for GCC compiler By Markus Levy, EEMBC and Ron Olson, IBM Corp
You can use industry-standard benchmarks to improve compiler performance.
