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Save valuable picoseconds using ECL-wired OR 5/15/2008
Substituting wire-OR connections for an XOR/XNOR ECL gate allows the circuit to meet stringent timing contraints.CPLD connects two instruments with half-duty-cycle generator 10/11/2007
A clocking circuit programmed into a CPLD generates a synchronizing pulse for a slower instrument at half the duty cycle of a faster instrument.VHDL program enables PCI-bus-arbiter core 9/13/2007
A simple VHDL program enables microprocessors or DSPs to act as PCI-bus masters.Use SystemVerilog for coverage metrics 3/29/2007
SystemVerilog constructs suit RTL design, high-level modeling, testbench creation, and assertion specification.ADVERTISEMENT
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