Aimed at 38-nm memory and 32-nm logic semiconductor high-volume manufacturing, Veldhoven, the Netherlands-based lithography giant ASML Holding NV today rolled out its Twinscan XT:1950i lithography system that uses a 1.35 numerical aperture lens, which the company claims increases the performance of its immersion chip lithography systems by 25% by improving overlay, resolution and throughput.
Meant to substantially reduce the amount of polysilicon used within the ingot-to-wafer manufacturing steps and eliminate some of the costly consumables in today’s wafer manufacturing, San Jose-based semiconductor, display, optoelectronics, and solar engineered substrate process technology provider Silicon Genesis Corp has produced solar substrates for photovoltaic applications using its “kerf-free” wafering process technology called PolyMax.
In a paper delivered at the International Conference on Electron, Ion, and Photon Beam Technology and Nanofabrication, eShuttle lifts the curtain on a technology shift that could take the e-beam technology far beyond the world of prototyping.
Renesas has joined IMEC's software defined radio front-end program to research new technologies for multi-standard RF transceivers and early realization of next-generation mobile phones.
Researchers at the University of California, San Diego led by Professor Edward Yu are working to create thin-film “single junction” solar cells with 45% sunlight-to-electricity conversion efficiencies by using nanostructures that scatter and channel light.
Following feedback from OEMs, microprocessor maker Advanced Micro Devices Inc detailed updates to its server roadmap to “strengthen its alignment with end-customer priorities,” by addressing platform longevity, performance-per-watt and virtualization features according to Randy Allen, AMD corporate VP and general manager for servers and workstations.
The move marks another advancement in IBM's quest to develop next-generation high-performance multicore computer chips that transmit information internally using pulses of light through silicon instead of electrical signals on copper wires.
To allow for optimization of system designs for timing, energy and yield versus expected application load, Leuven, Belgium-based nanoelectronics and nanotechnology research center IMEC demonstrated this week a variability-aware modeling flow that analyzes process variability of sub-45-nm technologies.