Design Center

Experts

Boeing postpones test flights again: How’s your tapeout looking? 11/12/2009

Boeing's recent issues offer a cautionary tale for any chip-design team engaged in a complex project.

Reference-tool flows and process-design kits, part two 11/12/2009

As a result of the shift to global design centers and the reduction in time designers spend on each process node, it is no longer always accurate to assume that experienced designers will be working with PDKs.

Openness and cooperation create healthy EDA ecosystem 9/29/2009

GUEST OPINION: Competition brings progress, but it helps the customer only if we respect standards and the need for interoperability.

Reference-tool flows and process-design kits, part one 9/17/2009

Reference-tool flows and process-design kits have been the basis of chip design since the start of the semiconductor industry. Although these files provide adequate information, they alone do not represent all of the issues.

SOI Industry Consortium stalks the “green thing” 8/20/2009

In some cases, the semiconductor's appeal to greeness makes sense, even without adding chlorophyll to the package epoxy.

Automation and the smiley face of death 7/9/2009

The pervasive trends of manpower reduction and the shift toward the use of foundry services have created a new set of challenges for designers attempting to bring a prototype design to reality.

Closing the ESL gap 6/16/2009

GUEST OPINION: Plenty of commentary has been written about the promise of ESL and how it remains unfulfilled. The truth is that engineers have been successfully designing with ESL tools for years.

A modest proposal for IP 6/11/2009

The US patent system needs fixing to the point that there are debates over just whose interests we should fix first.

Selecting the correct process geometry and options 5/14/2009

Most of the custom chips today, including ASICs, ASSPs (application-specific standard products), and special-purpose custom chips, have function blocks that do not require leading-edge processes.

"In-design" physical verification is "on-time" physical verification 5/11/2009

GUEST OPINION It's no longer practical to wait until the end of the physical design of an IC to do physical verification.

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