Design Center
In-Depth
Debugging FPGA designs may be harder than you expect 10/22/2009
Bugs can originate at every stage in the FPGA design flow; debugging success depends on using the right tools and methods.Implementing an all-digital PHY and delay-locked loop for high-speed DDR2/3 memory interfaces 10/15/2009
A new, all-digital approach to implementing high-speed PHY logic and a DLL offers a path to addressing increasingly stringent market requirements.IP quality lies beyond compliance testing 10/8/2009
Of course you want your standard-interface IP to pass compliance testing. But that accomplishment is just the beginning. Complete quality assurance for IP cores has far more challenges.FPGA architectural power-saving techniques at 40 nm 9/23/2009
As geometries shrink, FPGAs must begin to employ design-specific power-management techniques in order to save power while meeting timing.Outsourcing an IC design: Some advice from the trenches 9/3/2009
In this climate, outsourcing is becoming a mandatory skill for IC-design managers. But it's not intuitively obvious.Addressing interleaved multichannel memory challenges 8/20/2009
Interleaving addresses in multiple DRAM channels can greatly improve memory bandwidth, but it is not a trivial task.DRAM technology for SOC designers and—maybe—their customers 8/6/2009
An understanding of DRAM technology has become critical to anyone designing consumer-electronics SOCs.First-pass success in silicon packaging 8/6/2009
Package issues interact with all aspects of the design flow, from chip architecture to manufacturing decisions.Techniques for implementing high-performance processor cores 8/6/2009
Every step of the integration process gives the design team opportunities to move closer to its design goals.Dark side of the light 8/6/2009
Tales From The Cube: When a new design is exhibiting strange timing bugs, it can be difficult to decide where to begin your debugging. So, set it up on a testbench, hook it up to an oscilloscope, turn on a desk lamp, and get to work.ADVERTISEMENT
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