Design Center

In-Depth

Addressing interleaved multichannel memory challenges 8/20/2009

Interleaving addresses in multiple DRAM channels can greatly improve memory bandwidth, but it is not a trivial task.

DRAM technology for SOC designers and—maybe—their customers 8/6/2009

An understanding of DRAM technology has become critical to anyone designing consumer-electronics SOCs.

First-pass success in silicon packaging 8/6/2009

Package issues interact with all aspects of the design flow, from chip architecture to manufacturing decisions.

Techniques for implementing high-performance processor cores 8/6/2009

Every step of the integration process gives the design team opportunities to move closer to its design goals.

Dark side of the light 8/6/2009

Tales From The Cube: When a new design is exhibiting strange timing bugs, it can be difficult to decide where to begin your debugging. So, set it up on a testbench, hook it up to an oscilloscope, turn on a desk lamp, and get to work.

Making ASIC power estimates before the design 7/23/2009

A structured approach can give you meaningful power estimates when there's still time to influence process and architecture decisions.

Small-delay-defect testing 7/9/2009

SDD automatic-test-pattern generation breaks the nanometer-quality barrier.

Tackling formal assumptions through verification planning 7/7/2009

There are many tools for tracking assertions during verification, but what about the assumptions the design team has made about the design's environment? They need tracking too.

Little-known flash-memory features protect data and IP 6/25/2009

Features from block locking to encrypted-password-access mechanisms can prevent unintentional disruption, malicious damage, or copying.

Designing portability into silicon IP 6/11/2009

Design foundry portability into IP cores, rather than applying it after the fact.
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