News

Tanner EDA announces router, layout-device generator 9/3/2009

At the Design Automation Conference, which took place in July in San Francisco, Tanner EDA introduced the SDL (schematic-driven-layout) interactive autorouter and the DevGen layout-device generator. The company also announced that it is shipping Version 14.10 of its Tanner Tools Pro and HiPer Silicon products, which serve full-custom analog and MEMS (microelectromechanical-system) design.

Maskless copper deposition could slash metallization costs in ICs 9/3/2009

Whereas much rocket science goes into making the minimum-geometry metal lines at the bottom of the interconnect stack on an IC, no one pays much attention to making the upper metal layers on which the spacing is relaxed, the metal is thick, and some processes still use aluminum. A relatively new idea from Replisaurus could address those problems.

IBM Power7 architecture illustrates some issues for the rest of us 8/27/2009

By balancing execution speed, memory bandwidth and latency, and coherency overhead the Power7 architects have attempted to make possible systems that will scale up to 256 CPU cores without experiencing a sharp drop-off in performance-per-core. As such, the Power7 is not only a major stride in microprocessors for large systems, but a textbook on the lessons SOC designers will need to study in coming years.

Rotary-encoder IC meets all auto specs 8/20/2009

The AS5163 magnetic-rotary-encoder IC from austriamicrosystems satisfies the stringent automotive-IC-protection requirements in angle-sensing applications. The device provides overvoltage protection as high as 27V, and reverse-polarity protection withstands –18V reverse polarity at the supply pins.

ASIC demultiplexes to multiple displays from one DisplayPort signal 8/20/2009

HDMI (high-definition multimedia interface) and DVI (digital-video interface) transmit video data as continuous bit streams, whereas DisplayPort transmits the data in packets and allows for asymmetric two-way transfers. If your application is simply connecting a graphics chip to a display, packetizing creates a lot of overhead for little real benefit.

Start-up offers dynamically reconfigurable logic technology 8/6/2009

Start-up Akya is offering IP (intellectual property) to allow IC designers to include reconfigurable logic on their ASSPs (application-specific standard products) or ASICs (application-specific integrated circuits). The company delivers both reconfigurable-logic fabric and IP blocks to execute commonly required functions on that fabric.

Iron particle in nanotube may offer archival storage 8/6/2009

Researchers continue to seek out some plausible application for carbon nanotubes. The latest effort, by a team at the University of California—Berkeley, the Lawrence Berkeley National Laboratory, and Pennsylvania State University, has discovered that a multiwall nanotube containing a particle of iron might just be an effective archival storage device.

Accellera, Spirit Consortium merger hints at future of ESL design 6/11/2009

The merger aims to bridge the language-based design and IP-assembly worlds and will exploit the fact that the two organizations have been working in complementary areas of front-end design and verification.

Akya reveals dynamically reconfigurable logic technology 5/28/2009

IP-based offering reduces risk and increases flexibility of custom chip designs.

EUV prints critical layers for 22-nm SRAM 5/14/2009

IMEC (Interuniversity Microelectronics Center) reports having used ASML’s EUV (extreme-ultraviolet) Alpha lithography tool to print the contact and metal patterns for a 22-nm-node SRAM cell—apparently, the first application of the tool for multiple layers at this density. The SRAM cell is both tiny—at 0.

Power-supply modulation steps up handset-power-amp efficiency 4/9/2009

RF-engineering company Nujira has extended the reach of its efficiency-boosting technology for power amplifiers into the handset. The company has until now focused on the infrastructure side of communications, selling its HAT (high-accuracy-tracking) power-line modulators into applications such as base stations.

IMEC shows flexible packaged-IC assemblies 4/9/2009

Researchers at IMEC (Interuniversity Microelectronics Consortium) and at Ghent University recently demonstrated results from a 3-D integration process using highly thinned ICs with flexible packaging, materials to create fully flexible circuit assemblies. Researchers thinned an IC die to a thickness of 25 microns.

Simulator speeds eye measurements 4/9/2009

Agilent Technologies has introduced a 1 million-bit-per-minute signal-integrity channel simulator for multigigabit chip-to-chip data-link design. The channel simulator allows you to perform an interactive eye-diagram measurement from channel simulations within the ADS (Advanced Design System) signal-integrity design-and-analysis environment.

EDA revenues show unprecedented global decline 4/7/2009

Electronic Design Automation Consortium Chair and Mentor Graphics CEO Walden Rhines speaks exclusively with EDN on EDAC's Q4 and 2008 numbers, showing industry revenues down by almost 18% year over year for the final quarter. There were some bright spots in the numbers, however, including global employment in EDA and two industry categories that saw revenue rise during the year.

EDN names winners of 19th Annual Innovation Awards 3/31/2009

EDN has bestowed its 19th Annual Innovation Awards, honoring a diverse group of electronics engineers and the ground-breaking products they have produced. The Altera Stratix IV 40-nm FPGA design team is named Innovator of the Year. Read on for a complete list of the winners.

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