EDN's 19th Annual Innovation Awards Finalists

• 16X Data Rate enables high data rates (up to 12.8Gbps) at lower system clock and on-chip bus interface speeds.
•  Fully Differential Memory Architecture (FDMA) – enhances signal integrity and increases performance through point-to-point differential signaling of clock, data, and command/address (C/A), an industry first;
• FlexLink™ C/A – reduces pin count and increases scalability;
• Micro-threading – increases transfer efficiency and reduce power consumption; and
• Enhanced FlexPhase™ – enables the world’s highest memory signaling rates while simplifying routing and board design. 

These innovations enable Rambus’ XDR2 memory architecture to deliver data rates of 6.4 – 12.8 Gbps and a peak bandwidth of up to 51.2 GB/s from a single DRAM device. In addition, by offering architectural support of 12.8 Gbps data rates, along with XDR2 controller backward compatibility to XDR DRAMs, the XDR2 memory solution provides customers continuous compatibility with a path to performance upgrades and cost reduction. The XDR2 memory architectures is capable of providing twice the peak bandwidth per device when compared to a GDDR5-based system. Further, the XDR2 memory architecture delivers this performance at 30% lower power than GDDR5 at equivalent bandwidth.