Tapeout.html; Shakers

Reference-tool flows and process-design kits, part one
By Pallab Chatterjee, Contributing Technical Editor, 9/17/2009
Reference-tool flows and process-design kits have been the basis of chip design since the start of the semiconductor industry. Although these files provide adequate information, they alone do not represent all of the issues.

Automation and the smiley face of death
By Pallab Chatterjee, Contributing Technical Editor, 7/9/2009
The pervasive trends of manpower reduction and the shift toward the use of foundry services have created a new set of challenges for designers attempting to bring a prototype design to reality.

Selecting the correct process geometry and options
By Pallab Chatterjee, Contributing Technical Editor, 5/14/2009
Most of the custom chips today, including ASICs, ASSPs (application-specific standard products), and special-purpose custom chips, have function blocks that do not require leading-edge processes.

Mitigating tapeout risk
By Pallab Chatterjee, Contributing Technical Editor, 3/5/2009
Alleviate the risks inherent in tapeout by implementing automated sign-off, partnering with foundries, performing design application checking and statistical sensitivity analysis during physical verification, and targeting older process-technology nodes.

Physical design and architectural design
By Pallab Chatterjee, Contributing Technical Editor, 1/8/2009
The proliferation of deep-submicron processes has also led to an expanded tapeout scope, which now encompasses architectural design. Tapeout must address design trade-offs, such as power, I/O structures, memory structures, display interfaces, and programmability.

Mentor’s new DRC tool targets 32-nm node
By Pallab Chatterjee, Contributing Technical Editor, 12/5/2008
Mentor Graphics is enhancing its market-leading Calibre physical-verification environment for subwavelength-semiconductor processes with Calibre EQDRC (equation-based design-rule checking). The equations can be multivariable statements, which Calibre calculates dynamically using other measurement criteria, as part of the DRC.

Third-party IP: placement, blocks, and clocks
By Pallab Chatterjee, Contributing Technical Editor, 10/30/2008
Tapeout: Questions to ask IP providers regarding placement, rotation, embedded blocks, and clocks.

IP selection and power supplies
By Pallab Chatterjee, Contributing Technical Editor, 8/21/2008
The failure to fully embrace just one of the two competing power-analysis standards has caused confusion and uncertainty among IP users about power-strategy compatibility.

Third-party-IP providers: Physical-design questions, part two
By Pallab Chatterjee, Contributing Technical Editor, 6/26/2008
Engineers often overlook one physical-design issue for qualifying IP (intellectual-property) blocks: handling routing blockages and overlayer-routing conditions.

Third-party-IP providers: Physical-design questions, part one
By Pallab Chatterjee, Contributing Technical Editor, 5/15/2008
In addition to your architectural and performance goals, six categories of the physical view should be part of the selection criteria for the IP.

Know your IP provider
By Pallab Chatterjee, Contributing Technical Editor, 2/27/2008
Every SOC builder's checklist should include some IP-provider selection criteria.

Pcell and IP realities for fabless design
By Pallab Chatterjee, Contributing Technical Editor, 12/14/2007
A statistical-design approach suits systematic-design validation, allowing individual parameters without context.

Grid and resolution: Defining two critical terms in IC design
By Pallab Chatterjee, Contributing Technical Editor, 12/3/2007
Confusion and interchange of the terms "grid" and "resolution" has had a huge negative impact on the yield, reliability, and manufacturability of DSM (deep-submicron) and subwavelength semiconductor designs.

Reading skills for IC design: Tips for using descriptive text in EDA tools
By Pallab Chatterjee, Contributing Technical Editor, 8/16/2007
Current EDA tools allow long alphanumeric-string names, which, in turn, provide a great deal of flexibility in the area of self-documentation to the design engineer.

Where is the BOM in IC design?
By Pallab Chatterjee, Contributing Technical Editor, 7/19/2007
BOM (bill-of-materials) costs, along with approved vendor and provider lists, drive PCB-design tools and flows; IC-design flows have no such automated drivers.

Power and ground design
By Pallab Chatterjee, Contributing Technical Editor, 5/10/2007
IC and systems designers point to hand layout, SPICE analysis, and a design guru in a dark cube as the main solutions for power-grid sign-off.

Design verification, process technology...the wheel goes 'round again
By Pallab Chatterjee, Contributing Technical Editor, 3/1/2007
Recent technology and product announcements remind me of the saying, “Everything old is new again.” This phrase has been popping into mind more frequently as industry pundits herald new bottlenecks and incremental solutions to process- and design-tool issues as revolutionary. For design and EDA veterans, again hearing these discussions jogs the memory a bit.

In Tapeout, experienced physical design consultant Pallab Chatterjee offers case studies, observations, and hands-on personal experience on the technology and art of back-end IC design.