Guest Opinions

Openness and cooperation create healthy EDA ecosystem
By Nimish Modi, Cadence Design Systems, 9/29/2009
GUEST OPINION: Competition brings progress, but it helps the customer only if we respect standards and the need for interoperability.

Understanding power-over-Ethernet power allocation
By Daniel Feldman, Microsemi Corp, 8/10/2009
GUEST OPINION: Along with power-over-Ethernet's growing popularity has come growing demand for intelligent and efficient POE power allocation and management. In response, today's POE silicon suppliers have made sure that real-time power management is an integral part of virtually every enterprise-grade midspan and switch. Still, confusion about power-allocation best practices persists.

Closing the ESL gap
By Donald Cramb, EVE, 6/16/2009
GUEST OPINION: Plenty of commentary has been written about the promise of ESL and how it remains unfulfilled. The truth is that engineers have been successfully designing with ESL tools for years.

Transformational change: the revolution to come in electronics design
By Gerry Gaffney, Altium, 6/16/2009
GUEST OPINION: Like the proverbial comet-strike that wiped out the dinosaurs, the global recession has changed the climate for electronics. You’d better think about changing your organization’s design culture—and maybe your corporate culture—to adapt.

"In-design" physical verification is "on-time" physical verification
By Sanjay Bali, Synopsys Inc., 5/11/2009
GUEST OPINION It's no longer practical to wait until the end of the physical design of an IC to do physical verification.

One size fits all
By Justin Howard, Staccato Communications, 5/6/2009
GUEST OPINION: IEEE 802.11 WiFi is a technology that has taken a decade to mature and fit into a particular market segment.

For 10G interconnects, the RJ45 once again will dominate
By Bill Woodruff, Aquantia, 5/5/2009
GUEST OPINION: 10GBASE-T will be adopted as the primary 10GE interconnect for data-center switches and servers for many of the same reasons that RJ45 and twisted-pair cabling already dominate at gigabit speeds.

Innovating out of the downturn
By Dr. Mark Liu, TSMC, 4/23/2009
GUEST OPINION: If history is any indicator, innovation, not the business cycle, will pull the semiconductor industry out of recession. But this time young, innovative companies jumping on advanced processes may play a disproportionate role.

Verification methodology for low power: your blueprint to working silicon
By Krishna Balachandran, Synopsys, 4/10/2009
GUEST OPINION: The combination of voltage-aware verification tools and a verification methodology specific to low power will dramatically improve the chances for first-pass working silicon for low-power designs.

Design-centric yield management
By Sagar A. Kekare, Synopsys, 3/12/2009
GUEST OPINION: As process variations and design sensitivities interact at fine geometries, yield learning may depend not just on test coverage but on fast, accurate diagnosis of problems.

IP: final straw that broke the camel's back, or opening Pandora's box?
By Bill Martin, Mentor Graphics, 3/11/2009
GUEST OPINION: The future of intellectual property (IP) can be brighter with some work and support by all.

Forging new ground using existing COMs concepts
By Stephen Cunha, MEN Micro Inc., 1/23/2009
GUEST OPINION: Although highly popular embedded computing components that have been around for several decades, computers-on-modules (COMs) lacked the continuity needed to make these boards appeal to the various industries for which they were designed.

Reducing risk by integrating configurable mixed-signal data converters
By Lior Amarilio, ChipX, 12/2/2008
GUEST OPINION: An approach borrowed from the structured-ASIC world can be applied to mixed-signal data converters.

Making ASICs gel
By David Fritz, Silistix, 11/18/2008
GUEST OPINION: The enormous complexity possible in ASICs today has had a damping effect on design starts. Many in the industry simply can’t afford to design the chips their customers want, and that their foundries can easily fabricate. We postulate a design flow that, by focusing on identifying the customer’s behavior-level requirements and mapping them onto a proven platform, reduces design complexity and breaks the logjam in ASIC designs.

A new way to handle RF/PCB design
By How-Siang Yap, Agilent EEsof EDA, and Mark Forbes, Mentor Graphics, 10/23/2008
GUEST OPINION: EDA vendors collaborate to transfer RF circuit schematics and shapes into PCB tools and back again.

ESL: The state of the industry and what’s next?
By Ran Avinun, Cadence Design Systems, 8/19/2008
GUEST OPINION: While ESL continues to remain in its infancy, there are signs in the industry that point towards eventual mainstream usage, however the scope of what is needed has to be more inclusive of the entire system-level design and verification flow.

Your chip in half the time?
By Rajiv Maheshwary, Synopsys, 7/9/2008
GUEST OPINION: A project's commercial success depends on designers' ability to deliver silicon on time. That's why the industry recognizes the growing importance of time to results.

Freedom of choice: Harnessing the benefits of an open approach to system design
By Rob Evans, Altium, 6/13/2008
GUEST OPINION: Moving beyond a conventional IDE-based design flow can introduce a valuable expansion in the choices available to designers while providing innovative new ways to create embedded designs.

Voltage-aware simulation: No longer a fad, but a must for low-power designers
By Krishna Balachandran, Synopsys, 5/14/2008
GUEST OPINION: With multiple power domains, traditional on/off simulation loses accuracy and misses bugs.