Thermally Assisted Switching MRAM

Oct 23 2009 1:59PM | Permalink |Comments (0) |

Researchers at the Montpellier Laboratory of Informatics, Robotics and Microelectronics (LIRMM), in France, claimed they have developed a FPGA circuit based on non-volatile MRAM memory cell rather than the traditional volatile SRAM memory cells. LIRMM is a research entity of the University of Montpellier and the French National Center for Scientific Research (CNRS). Its activities include design and verification of integrated, mobile and communicating systems, and agent-based modeling of complex systems, as well as research on algorithms, bioinformatics, human-machine interaction and robotics.

This MRAM technology uses a Thermally Assisted Switching (TAS) MRAM, which utilizes a small current to heat the Magnetic Junction Tunnel to enable a higher sensitivity to magnetic fields. The magnetic field is then induced by a current line, which is typically located directly above or below the junction. The researcher commented stated that the main advantage of TAS compared to field-induced magnetization switching (FIMS) is that the current required to induce the magnetic field (between 5 to 10mA) is half that of FIMS.  The spokesperson indicated that the technique was equally valid for Spin Transfer Torque (STT) MRAM as well.

Adding FPGA circuitry to non-volatile MRAMs helps to overcome the drawbacks of classical SRAM-based FPGAs without incurring a significant speed penalty. The technology also supports the stacking of an MRAM memory array over the CMOS logic in a single chip, which supports permanent storage of data and configurations without consuming additional power. The combination also gains real value because FPGAs with nonvolatile memory would not require configuration loading at each power-up.

The first test chip has been made in CMOS 0.35µm for both the logic and the magnetic. The initial test chip contained basic blocks that successfully confirmed the performance claims—especially those regarding power consumption of the CMOS part—although the magnetic part is still under process. The second test chip, a 130nm CMOS part with a small magnetic junction FPGA, has been designed and is expected to be ready for processing within two to three months. This research is covered by a patent application and was funded by the French National Research Agency (ANR) through the CILOMAG project.

ANR also has a new project, for the design of a full FPGA MRAM by the French Institute of Fundamental Electronics, to include dedicated sensors for automotive and health applications. This FPGA is expected to reach the middle range of complexity of classical FPGA. The design is based on 130nm to 90nm for the logic circuitry and 90 nm for the TAS MRAM cells and should be in silicon by the middle of 2010.
 
A second test chip, using STT, is expected to be available in April 2010. Two companies—MENTA for the system level FPGA integration and Crocus Technology for its MRAM expertise—will participate in the design and manufacturing of that test chip.

While the available information indicates that these test chips are far from being commercialized or even fully qualified, we don’t see this as the most important element of the press release.

We think there are two important points to draw from the article. The first point is that the target application is once again the combination of high performance logic and high performance nonvolatile memory from the same manufacturing process and in the same die.

The second critical point of the press release is that the number of deep-pocket investment sources for new memory technologies continues to increase.