Reference Design

SP16160CH1RB High-IF Sub-sampling Receiver Subsystem Reference Design Kit

The SP16160CH1RB demonstrates a high-IF sampling receiver subsystem for use in wireless infrastructure systems. The subsystem includes the ADC16DV160 A/D converter, LMH6517 DVGA and LMK04031B precision clock conditioner.

Source: National Semiconductor
10/19/2009

The SP16160CH1RB demonstrates a high-IF sampling receiver subsystem that provides signal amplification, digitization and clocking as used in wireless infrastructure systems. The subsystem includes the ADC16DV160 analog-to-digital converter (ADC), LMH6517 Digitally-controlled Variable-Gain Amplifier (DVGA) and LMK04031B precision clock conditioner. The subsystem addresses multi-carrier, multi-standard wireless basestations addressing GSM/EDGE, WCDMA, LTE and WiMAX standards.

The SP16160CH1RB delivers an IF chain receiver sensitivity of -105 dBm, with a 9 dB carrier-to-noise ratio in a 200 kHz channel, at 192 MHz input IF. With the digitally-controlled variable gain amplifier (DVGA) set at a maximum gain of 22 dB, the sensitivity is limited primarily by the noise contribution of the DVGA. In the presence of a strong blocker, with the DVGA gain set at 12 dB and blocker level kept at 1.6 dBm input to the ADC, the SP16160CH1RB board delivers sensitivity of -86 dBm. In this blocking condition, the receiver sensitivity is determined by the ADC’s high spurious-free dynamic range (SFDR).

In the signal path, the subsystem provides impedance-matched, single-to-differential conversion through a 1:4 transformer and a 31.5 dB amplification gain range in 0.5 dB steps through the DVGA. The anti-aliasing filter at the output of the DVGA provides noise filtering and over 40 dB harmonic suppression by selecting the 20 MHz signal band centered at 192 Hz. The signal is then sampled and quantized by the ADC into 16-bit words using a 153.6 MHz CMOS clock.

In the clock path, a LMK04031B clock conditioning circuit operates with a 61.44 MHz reference oscillator and 76.8 Hz VCXO to provide the 153.6 MHz CMOS sampling clock. The clock output is also filtered and buffered to provide very low broadband noise for less than 200 fs total jitter over the clock input bandwidth of the ADC.

To simplify evaluation of the SP16160CH1RB, National offers the WaveVision 5.1 data capture board and WaveVision 5 software, which enables data capture and analysis, as well as complete programmable configuration of the ADC16DV160 and LMH6517 via a common serial peripheral interface (SPI) bus. Included with the SP16160CH1RB board, is a PIC loader board for configuring the LMK04031B.