The Xenergy tool provides a realistic way to estimate the overall energy impact of different processor configurations and extensions. It also helps software developers with energy-driven application code tuning on the overall processor plus memory subsystem. Detailed memory-system tuning can ensue and make a major difference in performance.

Processor core power specifications are based on simulations--vendors are free to delete or ignore any number of power-dissipating functions when reporting power numbers. Consequently, caution and judicious reading of the vendor data sheets are called for when comparing the power numbers for competing processor IP.

This white paper provides short descriptions of the most common hardware mechanisms--buses, direct connections, and data queues--used to interconnect processor cores on SOCs. For efficient communications, designers need to think outside the standard bus to get maximum performance.

Configurable-processor technology bridges the gap between a DSP's fixed-ISA flexibility and programmability and hard-wired power efficiency by enabling the creation of full-featured, programmable DSPs that have precisely the right features for a specific task. Tensilica’s Vectra LX--a fixed-point, vector DSP engine--illustrates this concept.

Tensilica's Diamond Standard Series is a family of 32-bit microprocessor and DSP cores. This paper explores the Diamond Standard Instruction Set Architecture (ISA) and the impact of architecture on performance and code density. It includes detailed benchmark discussions for comparisons to other architectures.