An introduction to the BER Contour measurement - what it is, how it is constructed, and why it is a valuable way of viewing parametric performance at gigabit speeds. Provides illustrative examples of BER Contour in action, taken with a SyntheSys Research BERTScope 12.5 Gb/s Signal Integrity Analyzer.

Clock recovery is a common part of many measurements, whether as part of a test setup or part of the device under test. We're going to look at clock recovery from a practical point of view, with emphasis on how it affects measurements. This document closely mirrors the poster "The Anatomy of Clock Recovery, Part 1."

Telecom Jitter Gen. measurement indicates jitter output at an optical interface & is a required test in standards such as SONET/SDH/OTN. BERTScope DCRj is a new instrument capable of this measurement. We compare results of the DCRj to the OmniBER jitter analyzer to demonstrate correlation & ability of the DCRj to measure new emerging data rates.

Examine the practical aspects of testing a limiting variant SFP+ transceiver for 8xFC apps. Covers requirements for Tx and Rx test points, including high speed serial electrical interface. Describes tests for compliance & testing methods. Pt 1 covers basic testing to standards, an overview of measurements, making them using BERTScope.

PCIe serial data rates of 2.5 & 5.0 GT/s require significant attention to signal integrity for successful compliance testing at two levels: Base Spec or Card EM. We describe testing to verify Rx compliance with the PCIe Base Spec, Rev 2.0 & highlight 3 areas: Jitter gen. incl. clock recovery, calibration channel, & compliance baseboard config.

There are considerable differences between 10GbE and 4xFC definitions of timing and amplitude settings for Rx jitter tolerance testing. Differences can be subtle, but have enormous impact on the test signal; therefore on test success. Points raised are equally applicable to other stressed eyes, both optical and electrical.

Many high-speed serial interface standards call for a test known as 'Stressed Eye.' This paper is an introduction to stressed eye testing, some of the high-speed standards that use it, and how a receiver test using stressed eye is constructed.

Much has been written about the strengths and weaknesses of dual-Dirac as a model for jitter measurement. This note gives a gentle introduction to the topic, and how dual-Dirac relates to practical measurements that can be made with sampling scopes and BER-based instruments.

Jitter can be defined very differently depending on context. We compare telecom standards (SONET/SDH/OTN) with enterprise & storage, explore eye diagram jitter compliance & different philosophies behind bathtub jitter vs. frequency banded jitter in other standards. Meas. examples illustrate implications for compliance & troubleshooting.

Clock Recovery is an important component in serial data measurements, whether evaluating the performance of transmitters, receivers or systems. If you spend considerable time trying to achieve jitter measurements which correlate, you will see how the contribution of clock recovery performance can improve your measurement integrity. Register today.