Today's FPGA designers are concerned about compilation times and achieving timing closure. To address these concerns, FPGA and EDA vendors are offering new incremental design and compilation capabilities, including design reuse, evolving designs, and engineering change orders, as well as team-based design flows.

This white paper details the power saving architecture innovations in the Stratix IV FPGA core and I/Os, in addition to processing techniques used to deliver the lowest power and highest performance at the highest densities. Compared to the nearest competing FPGAs, Stratix IV FPGAs are over twice the density, 35% faster, and consume 50% less total power--see how.

The 40-nm process offers clear benefits over prior nodes, including the 65-nm node and the more recent 45-nm node. Download this white paper to learn about the significance of 40-nm process technology, how Altera took advantage of leading test-chip practices, checkout procedures, and redundancy technology to improve device yields.

This detailed white paper provides technical specifications of new 40-nm FPGAs' performance, capabilities, and targeted applications. Chapters include "Trends and Requirements for High-Speed Links," "40-nm Process Node and Transceiver," "Mixed Signal Clock Recovery," "End-to-End Equalization," "Advanced Clock and Timing Generation," and "Power and Jitter."

View this 20-minute webcast to see how 40-nm FPGAs can help you reach new levels of SoC integration. You'll learn the three most important high-end digital system requirements, how transceiver quality affects system bandwidth, how to achieve power efficiency with high-end FPGAs, and more. View now!