<![CDATA[IC Design]]> 4442391 <![CDATA[Source synchronous interface timing closure]]> Mon, 18 Jul 2016 03:07 EDT 4442378 <![CDATA[Choosing a mobile-storage interface: eMMC or UFS]]> Thu, 14 Jul 2016 02:48 EDT 4442375 <![CDATA[The future of IC design]]> Thu, 14 Jul 2016 04:01 EDT 4442317 <![CDATA[FPGA constraints for the modern world: Product how-to]]> Mon, 04 Jul 2016 04:53 EDT 4442272 <![CDATA[Moving averager rejects noisy outlier values]]> Thu, 23 Jun 2016 04:23 EDT 4442196 <![CDATA[10 Ways to program your FPGA]]> Thu, 06 Oct 2016 03:47 EDT 4441916 <![CDATA[Control an FPGA bus without using the processor]]> Wed, 27 Apr 2016 07:44 EDT 4441689 <![CDATA[Timing-aware pipelining optimization for area reduction]]> Tue, 22 Mar 2016 08:06 EDT 4441647 <![CDATA[Large-panel QFN leadframes reduce costs but bring assembly challenges]]> Tue, 15 Mar 2016 05:36 EDT 4441611 <![CDATA[Software-defined FPGA computing with QuickPlay: Product how-to]]> Thu, 10 Mar 2016 01:50 EST 4441555 <![CDATA[Resolve picoseconds using FPGA techniques]]> Thu, 03 Mar 2016 07:57 EST 4441429 <![CDATA[NBTI’s impact on timing]]> Tue, 16 Feb 2016 07:06 EST 4441345 <![CDATA[Don’t over-constrain in formal property verification (FPV) flows]]> Sat, 02 Apr 2016 03:28 EDT 4441030 <![CDATA[Level-shifter block sips power]]> Sat, 12 Dec 2015 01:45 EST 4440967 <![CDATA[Improving fault coverage for random-pattern-resistant designs]]> Thu, 03 Dec 2015 07:53 EST 4440928 <![CDATA[The year of 3D memory]]> Mon, 12 Jan 2015 12:00 EST 4440892 <![CDATA[ADC SNR effects due to parasitics, mismatch, and noise]]> Mon, 23 Nov 2015 06:23 EST 4440822 <![CDATA[SoC PDN challenges and solutions]]> Thu, 12 Nov 2015 08:46 EST 4440802 <![CDATA[How formal verification saves time in digital IP design]]> Tue, 10 Nov 2015 04:48 EST 4440776 <![CDATA[Parametrized parallelized AMS testbenches speed detailed analysis]]> Fri, 06 Nov 2015 04:52 EST