<![CDATA[IC Design]]> 4441345 <![CDATA[Don’t over-constrain in formal property verification (FPV) flows]]> Sat, 02 Apr 2016 03:28 EDT 4441030 <![CDATA[Level-shifter block sips power]]> Sat, 12 Dec 2015 01:45 EST 4440967 <![CDATA[Improving fault coverage for random-pattern-resistant designs]]> Thu, 03 Dec 2015 07:53 EST 4440928 <![CDATA[The year of 3D memory]]> Mon, 12 Jan 2015 12:00 EST 4440892 <![CDATA[ADC SNR effects due to parasitics, mismatch, and noise]]> Mon, 23 Nov 2015 06:23 EST 4440822 <![CDATA[SoC PDN challenges and solutions]]> Thu, 12 Nov 2015 08:46 EST 4440802 <![CDATA[How formal verification saves time in digital IP design]]> Tue, 10 Nov 2015 04:48 EST 4440776 <![CDATA[Parametrized parallelized AMS testbenches speed detailed analysis]]> Fri, 06 Nov 2015 04:52 EST 4440770 <![CDATA[Making virtual prototypes work – A case study]]> Thu, 05 Nov 2015 04:06 EST 4440637 <![CDATA[PSI5 silicon validation setup is easily enhanced]]> Mon, 19 Oct 2015 03:55 EDT 4440596 <![CDATA[Best design practices for DFT]]> Wed, 14 Oct 2015 03:25 EDT 4440519 <![CDATA[Timing closure in multi-level partitioned SoCs]]> Wed, 07 Oct 2015 04:07 EDT 4440477 <![CDATA[Reuse UVM RTL verification tests for gate level simulation]]> Thu, 01 Oct 2015 06:08 EDT 4440445 <![CDATA[Post-silicon randomized functional testing finds corner-case problems]]> Mon, 28 Sep 2015 03:23 EDT 4440415 <![CDATA[Reducing IC power consumption: Low-power design techniques]]> Thu, 24 Sep 2015 02:39 EDT 4440402 <![CDATA[Aspects of IC power dissipation]]> Tue, 22 Sep 2015 12:24 EDT 4440286 <![CDATA[Ensure closure with proper latch constraints]]> Mon, 09 Mar 2015 09:54 EDT 4440222 <![CDATA[Reduce TNS/WNS in synthesis with individual path algorithm]]> Wed, 26 Aug 2015 03:28 EDT 4440201 <![CDATA[Save power in IoT SoCs by leveraging ADC characteristics]]> Fri, 21 Aug 2015 03:24 EDT 4440197 <![CDATA[PLL Subsystem architectures for SoC design]]> Fri, 21 Aug 2015 01:15 EDT