<![CDATA[IC Design]]> 4438062 <![CDATA[Anti-symmetric FIR filter slashes resource use]]> Mon, 22 Dec 2014 08:26 EST 4438051 <![CDATA[SoC clock monitoring issues: Scenarios and root cause analysis]]> Fri, 19 Dec 2014 01:38 EST 4438036 <![CDATA[Prevent quality mishaps using an automated SoC register access & reset verification]]> Thu, 18 Dec 2014 12:51 EST 4437944 <![CDATA[FPGA-based FSK/PSK modulation]]> Thu, 11 Dec 2014 09:02 EST 4437942 <![CDATA[Custom synchronization techniques for CDC paths]]> Thu, 11 Dec 2014 06:54 EST 4437919 <![CDATA[Product how-to: Achieving STARC and DO-254 compliance using HDL Coder-generated code]]> Tue, 09 Dec 2014 11:22 EST 4437795 <![CDATA[Fusion heats up]]> Mon, 01 Dec 2014 09:06 EST 4437759 <![CDATA[Delay-configurable standard cells with consistent footprints]]> Fri, 28 Nov 2014 10:19 EST 4437435 <![CDATA[Monolithic PWM generator runs fast, minimizes silicon]]> Mon, 17 Nov 2014 08:59 EST 4437354 <![CDATA[OPC modeling game changer: Rigorously-tuned compact modeling]]> Thu, 13 Nov 2014 02:49 EST 4437209 <![CDATA[Early detection of voltage drop and electromigration issues]]> Tue, 11 Nov 2014 06:00 EST 4436273 <![CDATA[IC mixed-mode verification: The Sandwiched-SPICE approach]]> Tue, 21 Oct 2014 03:33 EDT 4435976 <![CDATA[Burn-in 101]]> Tue, 14 Oct 2014 07:11 EDT 4435605 <![CDATA[Test cost challenges in LPCT (low pin count test) designs]]> Tue, 07 Oct 2014 07:33 EDT 4435372 <![CDATA[Faster integration verification for test vehicles using formal techniques]]> Tue, 30 Sep 2014 11:57 EDT 4435122 <![CDATA[Is FPGA power design ready for concurrent engineering?]]> Wed, 24 Sep 2014 08:34 EDT 4435079 <![CDATA[Product how-to: Reliable SoC bus architecture improves performance]]> Tue, 23 Sep 2014 11:24 EDT 4434919 <![CDATA[Design faults leading to clock and data glitches]]> Fri, 19 Sep 2014 04:12 EDT 4434857 <![CDATA[Low-loss compression of CPRI baseband data]]> Wed, 17 Sep 2014 10:23 EDT 4434601 <![CDATA[Blind assembled samples enable early customer testing]]> Fri, 12 Sep 2014 07:35 EDT