<![CDATA[IC Design]]> 4438950 <![CDATA[RTL coding architecture affects power estimation & analysis]]> Tue, 17 Mar 2015 06:19 EDT 4438937 <![CDATA[Handle SEUs with C-slow retiming]]> Mon, 16 Mar 2015 08:07 EDT 4438914 <![CDATA[Design compilation in hardware emulators]]> Fri, 13 Mar 2015 02:27 EDT 4438908 <![CDATA[What’s stopping pre-silicon emulation from covering the last mile?]]> Thu, 12 Mar 2015 09:58 EDT 4438873 <![CDATA[18 Views of ISSCC]]> Tue, 03 Nov 2015 02:37 EST 4438799 <![CDATA[Time for multimedia SoCs to get their analog signals right]]> Fri, 03 Apr 2015 03:15 EDT 4438760 <![CDATA[Interconnect (NoC) verification in SoC design]]> Fri, 27 Feb 2015 07:30 EST 4438635 <![CDATA[Sequential clock gating maximizes power savings at IP level]]> Fri, 02 Oct 2015 11:26 EDT 4438600 <![CDATA[Image compression overview]]> Tue, 02 Jun 2015 07:01 EDT 4438338 <![CDATA[Timing challenges for serial flash interface]]> Tue, 13 Jan 2015 07:09 EST 4438319 <![CDATA[Stressing of redundant memory bits during burn-in test]]> Tue, 01 Dec 2015 11:32 EST 4438124 <![CDATA[1969 Compucorp calculator teardown]]> Mon, 29 Dec 2014 05:55 EST 4438062 <![CDATA[Anti-symmetric FIR filter slashes resource use]]> Mon, 22 Dec 2014 08:26 EST 4438051 <![CDATA[SoC clock monitoring issues: Scenarios and root cause analysis]]> Fri, 19 Dec 2014 01:38 EST 4438036 <![CDATA[Prevent quality mishaps using an automated SoC register access & reset verification]]> Thu, 18 Dec 2014 12:51 EST 4437944 <![CDATA[FPGA-based FSK/PSK modulation]]> Thu, 11 Dec 2014 09:02 EST 4437942 <![CDATA[Custom synchronization techniques for CDC paths]]> Thu, 11 Dec 2014 06:54 EST 4437919 <![CDATA[Product how-to: Achieving STARC and DO-254 compliance using HDL Coder-generated code]]> Tue, 09 Dec 2014 11:22 EST 4437795 <![CDATA[Fusion heats up]]> Mon, 01 Dec 2014 09:06 EST 4437759 <![CDATA[Delay-configurable standard cells with consistent footprints]]> Fri, 28 Nov 2014 10:19 EST