<![CDATA[IC Design]]> 4439512 <![CDATA[Matrix-based clock verification uncovers SoC bugs]]> Wed, 20 May 2015 06:00 EDT 4439490 <![CDATA[Reverse bias techniques for high-end automotive microcontrollers & low leakage]]> Tue, 19 May 2015 03:20 EDT 4439464 <![CDATA[The 7 levels of IP verification]]> Fri, 15 May 2015 05:48 EDT 4439435 <![CDATA[Three ways the 3-terminal resistor model improves power converter circuits]]> Wed, 13 May 2015 02:01 EDT 4439344 <![CDATA[Simplified kurtosis computation detects signal interference]]> Sun, 05 Apr 2015 07:26 EDT 4439299 <![CDATA[Mixed-mode verification of DDR, LCD, and memory sub-systems: Verilog-AMS vs. SPICE]]> Thu, 30 Apr 2015 11:28 EDT 4439289 <![CDATA[Security architecture for automotive microcontroller flash memory]]> Fri, 24 Apr 2015 09:08 EDT 4439239 <![CDATA[Verilog-AMS vs. SPICE view: An SoC verification comparison]]> Sat, 18 Apr 2015 08:57 EDT 4439203 <![CDATA[Robust asynchronous-reset architecture for scan coverage]]> Wed, 15 Apr 2015 10:34 EDT 4439188 <![CDATA[Validating MEMS and other sensors]]> Tue, 14 Apr 2015 03:01 EDT 4439180 <![CDATA[Product How-to: Fully utilize TSMC’s 28HPC process]]> Mon, 13 Apr 2015 04:53 EDT 4438950 <![CDATA[RTL coding architecture affects power estimation & analysis]]> Tue, 17 Mar 2015 06:19 EDT 4438937 <![CDATA[Handle SEUs with C-slow retiming]]> Mon, 16 Mar 2015 08:07 EDT 4438914 <![CDATA[Design compilation in hardware emulators]]> Fri, 13 Mar 2015 02:27 EDT 4438908 <![CDATA[What’s stopping pre-silicon emulation from covering the last mile?]]> Thu, 12 Mar 2015 09:58 EDT 4438873 <![CDATA[18 Views of ISSCC]]> Tue, 03 Nov 2015 02:37 EST 4438799 <![CDATA[Time for multimedia SoCs to get their analog signals right]]> Fri, 03 Apr 2015 03:15 EDT 4438760 <![CDATA[Interconnect (NoC) verification in SoC design]]> Fri, 27 Feb 2015 07:30 EST 4438635 <![CDATA[Sequential clock gating maximizes power savings at IP level]]> Fri, 02 Oct 2015 11:26 EDT 4438600 <![CDATA[Image compression overview]]> Tue, 02 Jun 2015 07:01 EDT