<![CDATA[IC Design]]> 4440029 <![CDATA[DDR interface gate-level simulation advantages]]> Tue, 28 Jul 2015 07:53 EDT 4440025 <![CDATA[MEMS & self-assembled monolayers: Protecting and functionalizing next-gen devices]]> Tue, 28 Jul 2015 04:20 EDT 4439943 <![CDATA[DDR simulation strategy catches bugs early]]> Thu, 16 Jul 2015 08:51 EDT 4439878 <![CDATA[Debugging LBIST safe-stating issues]]> Fri, 07 Aug 2015 07:09 EDT 4439851 <![CDATA[Detect SoC feature/protocol pin limitations across packages]]> Mon, 06 Jul 2015 06:59 EDT 4439849 <![CDATA[Efficient checks for cache-coherency verification in complex SoCs]]> Mon, 06 Jul 2015 12:58 EDT 4439841 <![CDATA[Detect SoC pin-multiplexing conflicts early]]> Sat, 07 Mar 2015 05:47 EST 4439814 <![CDATA[8 FD-SOI questions you're afraid to ask]]> Tue, 30 Jun 2015 12:18 EDT 4439803 <![CDATA[Memory fault models and testing]]> Mon, 29 Jun 2015 01:08 EDT 4439751 <![CDATA[Reducing chip IR drop in backward-compatible power bar-limited LQFP SoCs]]> Mon, 22 Jun 2015 04:07 EDT 4439723 <![CDATA[Methodology improves SoC power grids]]> Wed, 17 Jun 2015 02:48 EDT 4439637 <![CDATA[Documentation First! unifies design flow]]> Mon, 08 Jun 2015 02:05 EDT 4439626 <![CDATA[Structural netlist efficiently verifies analog IP]]> Thu, 04 Jun 2015 07:53 EDT 4439601 <![CDATA[Intel/Altera deal is real]]> Tue, 02 Jun 2015 12:17 EDT 4439512 <![CDATA[Matrix-based clock verification uncovers SoC bugs]]> Wed, 20 May 2015 06:00 EDT 4439490 <![CDATA[Reverse bias techniques for high-end automotive microcontrollers & low leakage]]> Tue, 19 May 2015 03:20 EDT 4439464 <![CDATA[The 7 levels of IP verification]]> Fri, 15 May 2015 05:48 EDT 4439435 <![CDATA[Three ways the 3-terminal resistor model improves power converter circuits]]> Wed, 13 May 2015 02:01 EDT 4439344 <![CDATA[Simplified kurtosis computation detects signal interference]]> Sun, 05 Apr 2015 07:26 EDT 4439299 <![CDATA[Mixed-mode verification of DDR, LCD, and memory sub-systems: Verilog-AMS vs. SPICE]]> Thu, 30 Apr 2015 11:28 EDT