Chip-core protection: everybody's business By Jim Lipman, Technical Editor
Anyone involved with core-based chip design-core vendors, chip designers, and chip fabricators-should be concerned about protecting chip cores from unauthorized use. Although still in their early stages, the tools and techniques for conveying core-design data and tracking core usage are developing rapidly.
FROM EDN EUROPE: System-level design languages: to C or not to C?
Graham Prophet, Editor, EDN Europe
First the bad news: If you have only recently begun to fully exploit HDL-based design with VHDL or Verilog, it will soon be time to move on and move up to a higher level of abstraction. But the good news is that the languages you'll be using may not be entirely new, and they might even be very familiar.
Design Features
Squash your embedded debugging time By Warren Webb, Technical Editor
Each new embedded product brings increased software complexity, yet market pressures dictate a shorter debugging time. Make sure you have the right weapons and an effective plan of attack before entering your next big bug battle.
As edge speeds increase, wires become transmission lines James Sutherland, California Micro Devices
EEs must learn when interconnections among circuits behave as transmission lines, which can unexpectedly alter signals. Systems whose designs ignore these effects perform poorly or fail altogether.
Track down intermittent faults with your DSO, ICE, and logic analyser
W Farnbach, Conexant Systems; J Ganssle, Consultant; and W Swift
Intermittent failures are the most difficult to track down, especially when they cross domains. You need several tools to detect and fix cross-domain faults. Using new DSO-trigger capabilities, you can detect a fault and trigger your emulator, logic analyzer, or both to find the source.
