John Bass's profile
John Bass is a seasoned hardware/software developer and consultant, with over 40 years of industry experience, in a broad span of industry applications. Formal education is diverse with Business, Science, Statistics, Electrical Engineering, and Computer Science training over 11 years, resulting in a B.S. Computer Science from CalPoly, San Luis Obispo. Something like a computer engineering degree, with a strong science and business background. Extensive industry experience with drivers, porting, and operating systems, combined with hardware/software/firmware development of server level systems, embedded systems, motion control systems, and robotics. Other experience includes Reconfigurable Computing applications with Xilix FPGA's, 802.11 mesh networks, and Canopy Wireless networks.
- Funniest schematic ever
- Hmm ... EDN as a for-profit company, selling industry information, just had a staff blogger use this schematic for commercial gains :( Welcome to the real world
- Moving to open-source PCB design
- The exceptions to this are Creative Commons Attribution-NonCommercial-NoDerivs CC BY-NC-ND which attempts to provide your customers access, without fully handing to the design to your competitors. This does not mean that your product will NOT be copied and resold, as it very well may be since you are handing a lot of IP to your customers. What it does mean, is that someone will have to do some significant re-engineering around your design, and that you will have some recourse in US or EU courts, but little control in the rest of the world.
- RTL synthesis requirements for advanced node designs
- The drive for smaller geometries often includes board level optimizations of combining multiple packages into a single package for both cost reduction, and removing off die interconnect latencies which are significantly higher than on-chip. The "Because we have always done it THAT way" approach will always force teams into difficult corners some day, as underlying assumptions in core design rules change. So get over it, and make the changes necessary to move the team forward. Locality is everything in minimizing interconnect lengths and associated latencies. Breaking large monolithic designs in smaller functional units that are pipelined, may allow functional units to run at higher clocks, than degrading everything for die wide skew. Using 10 layer Manhattan layout restricted to H and V directions (as shown in the example) increases interconnect lengths significantly in some designs. Having layers that are diagonals, and "all direction" can improve some designs significantly. Longer traces may need to be wider (lower resistance per length) in some cases. This works well for long diagonals mating to H and V interconnect points. There are many other optimizations available, once the chains of "because we have always done it THAT way" are broken.
- That 60W-equivalent LED: What you don’t know, and what no one will tell you…
- So what's the engineering problem here? just need to create some air flow the transfer the heat from the led chips to the enclosure. www.engadget.com/2012/12/12/ge-dual-piezo-jets/
- An energy-harvesting scheme that is nearly useless?
- Completely remove the "MIT" branding, and what merits are left? The remote environmental sensor platform doesn't bring high value to the market place.
- Are EVs safer than gas-powered cars?
- Gasoline has a pretty meek flame temp, of about 1,024C ... in comparison, the temp of an electric arc flash can exceed 19,000C and generate a super heated plasma that is useful for cutting or incinerating a lot of things that don't otherwise burn easily. Doesn't even require that many volts or amps, to have a super hot plasma like this ignite everything around it. Lessons learned from plasma cutting torches.