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- Improve FPGA project management/test by eschewing the IDE
- I understand how it's convenient to use scripts can be helpful. For Vivado when using AXI components, the GUI is how everything is configured and setup and connected. Then vivado generates the code for you in the project directory. I've used vivado's tool to save a project and re-generate it with a tcl "build" script, but I don't have the src code until afterwards. This script is still really running gui tcl commands, just not showing you the gui. Your article seems to imply you have your hdl files already saved somewhere, but my axi based project directory doesn't have them until you run the "build" script in vivado. When I run the script it generates the hundreds of files I want to avoid putting into SCCL. Bottom line question: How are you building a source file list without having vivado first create the bloated project content? If you're not running vivado to build the project, how do you get src files that connect and configure all the AXI blocks (without doing that by hand)? If you're actually building a project first and then calling out the project files as your src list, then this seems like it's not a "non-project" mode, it's more of a "batch mode" What are your thoughts?