How to overcome memory-imposed access rates and bandwidth constraints

-January 13, 2014

Design teams building high-speed, next-generation network communications equipment suffer under the constraints imposed by memory. Some design solutions use only on-chip memory which is inherently limited in capacity and competes with silicon area that could be otherwise used for computation or other functionality. More complex applications require external memory and at the processing rates available today need the highest possible random access rate to that memory.  Traditional memory interfaces are a burden to performance because they are plagued by slow speeds, lengthy latency, and high pin counts.  As a result, conventional design approaches to implementing external memory have already reached the point of diminishing returns.

 

Serial Protocols & Standards Break the I/O Bottleneck

Consider any modern System-on-Chip (SoC) available today and you will see nearly all the interfaces are serial, except for that to traditional memory ICs. Going forward, the transition to serial memory has already begun and decisions need to be made regarding which serial interface protocols to support. Any interface can be delineated into its physical layer or PHY, transport protocol or PCS, and transaction layer or the command set. Standardization can take place on each level independently.

 

Regarding the serial PHY; the industry standards group, the Optical Internetworking Forum (OIF), published the Common Electrical Interface I/O (CEI) standards including CEI-11 in September 2011.1 Standards development groups such as OIF require three to five years to develop channel models, set clocking and jitter budgets, determine electrical signal coding, and encourage the development of the ecosystem. As a result, these standards are being adopted for a broad range of applications.

 


In fact, three serial memory interface protocols have adopted the CEI-11 physical definition: the GigaChip Interface (GCI) 2, the Interlaken Look-Aside (ILA) 3, and the Hybrid Memory Cube Interface (HMC) 4 as indicated in Fig. 1 above. Design teams can expect these protocols to also conform to the CEI-25 5 standard in the future. Each of these protocols targets different applications and markets as outlined in Table 1 below.

Designers therefore do not need to develop three different interface solutions to meet multiple use cases. Instead, host processors can incorporate two or more protocols running on the same physical layer. The interface need not be limited to memory but could also be used for general serial IO, giving the ultimate flexibility to the system designer in addressing a broad range of market applications.

Although it is possible to multiplex the protocols, a close look reveals distinct performance differences. Protocols leveraged from other applications result in unnecessary overhead and latency when used in point to point applications, such as a high performance memory interface. It may be necessary in the near term to include all three serial protocols on the SoC processor in order to support performance capabilities and devices from different manufacturers.  If a customer wants to consolidate to two or one interface only GCI offers high efficiency for all the memory access patterns used on high performance networking line cards..

 

Understanding Networking Line Card Requirements

Networking applications tend to have three types of memory access patterns, depending on the function being performed.  The first is a buffer application, where there is a fixed 1:1 ratio of reads to writes with low data persistence. A packet arrives and needs to be stored for a short amount of time until it can be dispatched to the next leg of its journey.  Depending on the end market, packet buffers might be implemented with or without error correction in the array. If for some reason the packet is corrupted there is almost always an option inherent in networking to drop the packet which will trigger a retransmit from the origin. The process of packet buffering involves either high packet arrival rates for sizes in the sub-64B range, or long lived ‘elephant flows’ of large or jumbo (9KB) transmissions. Efficiency is paramount, but also the ability to accommodate a wide range of packet sizes is necessary.  Figure 3 compares the efficiency of data transfer in a packet buffer application, including all the necessary overheads of commands and transport.

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