Design with QDR-IV for high-performance networking systems, part 2
QDR-IV SRAM was designed to provide best-in-class random transaction rate (RTR) performance to satisfy demanding network functions. In this process, bus turnaround time plays an important role in determining if an additional interval is required between the read and write commands to avoid bus contention on the same I/O port.
Let us consider a write command followed by a read command on Port A in QDR-IV HP SRAM. The write data is supplied to the DQA pins exactly three clock cycles from the rising edge of the CK signal corresponding to the cycle when the write command was initiated. The read command can be issued in the next cycle as the data would be available on DQA pins after five clock cycles from the rising edge of the CK signal corresponding to the cycle when the read command was initiated. We still have two extra cycles, which will be useful to accommodate the bus turnaround time and trace delay (from ASIC/FPGA to QDR IV memory). Therefore, the read command can be initiated right after the write command.
In other cases, if the write command follows the read command, the write command should be issued three clocks after the read command. This is because the read data on DQA pins would appear five clocks after the read command is sampled at the rising edge of the clock signal CK, and the write data is supplied to the DQA pins exactly three clock cycles after the write command is sampled at the rising edge of the clock signal CK. Otherwise, there will be bus contention. Therefore, the minimum clock cycles after which a write command should be issued is given by RL – WL + 1 (RL: Read latency; WL: Write latency, both measured in clock cycles). The extra one cycle is to allow for the data to be captured correctly and compensate for the bus turnaround delay (usually one clock cycle).
If the trace delay is more than the bus turnaround delay, then the interval between ‘Read to Write’ commands is given by:
In Figure 1, the write command on port A is issued after four clock cycle from the read command. This is done to avoid bus contention due to the difference in read and write latencies, bus turnaround time, and trace delay.
Figure 1 This diagram shows QDR-IV HP SRAM timing analysis.
QDR-IV devices support bus inversion feature to reduce switching noise and I/O power. In a memory transaction, either the memory controller or the QDR-IV could choose to apply bus inversion.
Because the pseudo open drain (POD) signaling mode in QDR-IV device provides an option for I/O signals with high-side termination to VDDQ, signals driven to a logic HIGH state consume zero power. Therefore, if more than half of the bits in a transaction are zero, bus inversion is a good feature to use with POD I/O signaling. Note that internally QDR-IV takes care of data integrity for inverted address and data bus.
The address and data bus inversion features can be enabled or disabled using chip-configuration registers.
Address bus inversion
The AINV is a double data rate signal and is updated for each address sent to the memory device. The AINV pin indicates whether the address bus (An – A0) and AP are inverted. AINV is an active HIGH signal. When AINV = 1, the address bus is inverted; when AINV = 0, the address bus is not inverted. The function of the AINV pin is controlled by the memory controller.
The address bus and the address parity bit are considered together as address group (AG). Table 1 lists the AG definitions and AINV setup conditions for x18 and x36 QDR-IV options.
Example of x36 device
Without address bus inversion
Assume that you want to access the 22’h 000199 and 22’h 3FFCFF addresses respectively. The 17 address pins need to switch the logic state between the first and second addresses, as shown in Table 2 (red cells). This increases the switching noise, I/O current, and crosstalk on the address pins.
With address bus inversion
According to Table 1, the 1st address group (22'h 000199) satisfies the inversion logic condition. Therefore, before the memory controller transmits the 1st address group, it will invert the address group (22’h 000199 --> 22’h 3FFE66) and set the AINV pin to 1. Because the 2nd address group does not need to be inverted, the memory controller transmits it with no change and AINV is set to 0.
Table 3 shows the result with address bus inversion. You can now see only five address pins need to switch the logic (see the red cells). Therefore, the total number of switching bits is reduced to five, which results in reduced simultaneous switching output (SSO) noise, I/O current, and crosstalk. Thus, the address bus inversion feature supported by QDR-IV helps reduce the effect of switching noise.