Design with QDR-IV for high-performance networking systems, part 3

& -March 10, 2017

Read part 1 of this series, which discusses the two types of QDR-IV memory, clocking, read/write operations, and banking, and part 2 on important bus issues such as bus turnaround, bus inversion, and address parity.  

QDR-IV’s high RTR, coupled with differentiated features such as dual bidirectional ports, ECC, bus inversion, ODT, and address parity, make it an excellent solution for networking systems

Deskew training sequences

The high frequency at which the memory controller and QDR IV operate means that the data valid window is very narrow. The QDR IV device supports a feature called “deskew training sequence” that helps improve this data valid window period by reducing the skew between byte lanes. This results in better timing margins for the controller when reading data from the memory. This training sequence is an important part of the initialization process of Cypress’s QDR-IV SRAMs. This training sequence is usually employed by applications that do not support inbuilt de-skew functionality. The training sequence is illustrated in Figure 1.


Figure 1 The deskew training sequence reduces the skew between byte lanes.

Deskew training sequence is part of the initialization procedure. Immediately after the power-up and reset sequences, the controller must set the write_train_enable bit (bit location 7) in the option control register during the configuration mode of operation. By doing so, the controller can avoid re-entering the configuration mode before the training sequence. Setting this bit does not have any influence until the read data deskew training.

Deskew is achieved in three steps:
  • control/address deskew
  • read data deskew
  • write data deskew

Control/address deskew

Set LBK0# and LBK1# to corresponding bit values depending on the signal to be de-skewed. See Table 1 for loopback signal mapping. Thirty-nine input signals are looped back to data pins of port A. Based on LBK0# and LBK1# status, at a time thirteen input signals are mapped to DQA0-DQA12.   

Table 1 Loopback signal mapping


The clock inputs DKA0, DKA0#, DKA1, DKA1#, DKB0, DKB0#, DKB1 and DKB#1 are free-running clock inputs and should be continuously running during the training sequence.

Each input pin is sampled on both the rising and falling edges using the input CK/CK#. The output value on the rising edge of the output QKA/QKA# will be the value that was sampled on the rising edge of the input clock. The output value on the falling edge of the output QKA/QKA# will be the inverted value of what was sampled on the falling edge of the input clock. Data inversion is not active in this mode and CFG# will be HIGH during address/control loopback training.

As shown in Figure 2, if the address/control signal is not de-skewed, the signal on DQA, which should remain HIGH throughout the training period, will go low. This signal transition should be captured by the module driving the signals and the controller must calibrate the signal accordingly.


Figure 2 In this loopback training diagram, if the address/control signal is not de-skewed, the signal on DQA will go low.

Read data deskew

At this stage, the address, control, and data input clock are already de-skewed. During the read data deskew sequence, the training data pattern that is used to write into the memory is held at a constant value (D00,D01,D20,D21) as shown in the waveform diagram in Figure 3. Both LBK0# and LBK1# are set to 1 during this training sequence.

Write_train_enable bit is set to 1 while configuring the option control registers. The first and second data burst are sampled from the same data bus, but the second data burst is complemented before writing into memory. The write_train_enable bit has no effect on the read data cycles.

After the data pattern is written into the memory, standard read commands allow the memory controller to access the data and de-skew with respect to QK/QK#. DINVA/DINVB will be ignored during write and always toggles during read when write_train_enable = 1.

As shown in read data deskew diagram below (Figure 3), the data written to memory (D00,D01,D20,D21) is  all 1s and the corresponding read data (Q00,Q01,Q20,Q21) toggles between 1 and 0. The controller must capture the toggled data and verify. Otherwise, a precise calibration is required to confirm read data de-skew from the controller.


Figure 3 The read data deskew sequence diagram shows the data written to memory is  all 1s and the corresponding read data toggles between 1 and 0.

Write data deskew

By this time, the address, control, clock, and data outputs are already de-skewed. Before performing the write data deskew sequence, enter the configuration mode again to disable write_train_enable by setting the corresponding bit to 0.

Write data deskew is performed using write commands to memory followed by read commands in the normal operation mode. The de-skewed read data path is used to determine whether the write data was received correctly by the device. This permits the controller to de-skew the following signals with respect to DK/DK# input data clocks: DQA, DINVA, DQB, and DINVB.



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