“Hippasian” nonlinear VFC stretches dynamic range

-February 19, 2009

Hippasus of Metapontum was a Greek philosopher who lived approximately 500 BC. A disciple of Pythagoras, Hippasus discovered some interesting properties of square roots. This Design Idea describes a VFC (voltage-to-frequency converter) that also uses an interesting property of square roots: their ability to extend VFC dynamic range by orders of magnitude (Figure 1).

Linear VFCs are one of the oldest types of ADCs, and their simplicity and noise rejection preserve their popularity. However, their Achilles’ heel is the direct proportionality between dynamic range and conversion time. Because the voltage resolution of linear VFC conversion is equal to the full-scale voltage reference, VREF, divided by full-scale frequency, fFS, multiplied by the counting interval, large dynamic range is inevitably associated with long counting intervals and slow conversion, even when clever VFC design provides for fast full-scale frequency.

For example: If you use a 3-MHz VFC-based ADC, such as Analog Devices’ AD7742 with a 2.5V reference voltage in a design that requires 1-mV resolution, then you would need a minimum counting interval of 2.5/1 mV/3 MHz=2500/3 MHz=833 μsec. That counting interval yields only 1200 conversions per second, which for many applications is inconveniently slow.

The “Hippasian” VFC avoids this problem with a semiparabolic-transfer function instead of a linear one. It works by substituting VREF2, which, instead of the constant VREF of a linear VFC, is proportional to the output frequency. Then, VREF2=VREF×fOUT/fFS, fOUT=VIN×fFS/VREF2=VIN×fFS/(VREF×fOUT/fFS), (fOUT/fFS)2=VIN/VREF, and fOUT=fFS×(VIN/VREF)1/2.

Generating the dynamic, output-frequency-proportional reference voltage is the job of op amps A1, which boosts the VFC’s internal 2.5V reference to power flip-flop Q1, and Q1 and A2, which compose a high-performance frequency-to-voltage converter. The accuracy of the reference voltage depends on precise 50-to-50 symmetry of the VFC’s input-clock reference. Flip-flop Q2 guarantees this symmetry.

The effect on conversion resolution of low-level signals is dramatic. To return to the example of a 2.5V full-scale, 1‑mV-conversion resolution, which requires a 2500-count, 833-μsec conversion interval with a linear 3‑MHz VFC, the Hippasian version needs only 100 counts and 33 μsec—a 25-fold improvement. Software linearization of the Hippasian VFC conversion is easy, requiring only one multiplication.

Loading comments...

Write a Comment

To comment please Log In