Read isolated digital signals without power drain

-November 25, 2004

Although optocouplers offer designers a straightforward method of establishing galvanic isolation between circuits that operate at different ground potentials, they do not provide an ideal approach. An optocoupler draws power from the isolated circuit, switches relatively slowly, and loses current-transfer ratio as its light emitter ages.

The circuit in Figure 1 overcomes these limitations by replicating a digital signal's state, drawing no power from the isolated input, and consuming only modest power on the nonisolated side. As Figure 2 shows, the circuit imposes only a 20-nsec input-to-output delay from the positive edge of SENSE_CLK to DATA_OUT.

MOSFET transistor Q1 operates in either of two states—high resistance between source and drain (RDS/OFF), or low resistance (RDS(ON)) when a control signal drives Q1 into conduction. When conducting, Q1 imposes a low resistance across T1's secondary winding, W3. The remainder of the circuit senses the state of T1's secondary resistance. Resistor R1, capacitor C1, and the complementary inputs of MOSFET-driver IC1 differentiate the SENSE_CLK signal's positive-going input edge, producing a positive-going 5V pulse at IC1's output and driving one end of winding W1. Figure 2 shows the relationship among the circuit's signals.

Connected in series-aiding mode, the two primary windings W1 and W2 of T1 form a 2-to-1 inductive voltage divider whose center tap drives the inverting input of IC3, a high-speed comparator. With Q1 off and thus presenting an open circuit across the secondary of T1, the junction of windings W1 and W2 applies a pulse of approximately 2.5V to comparator IC3's inverting input and drives IC3's internal state low. Meanwhile, IC2's two gates, resistor R2 and capacitor C2 generate a short strobe pulse in the middle of IC1's output pulse and applied to IC3's LE (latch-enable) input.

Latching IC3's internal state to its external output (DATA_OUT) produces a logic-low output that follows DATA_IN. If DATA_IN goes sufficiently positive to bias Q1 on, Q1's low resistance across W3 reflects a low impedance to windings W1 and W2 of T1. The reduced pulse amplitude at the junction of W1 and W2 and IC3's inverting input of approximately 0.5V is insufficient to trigger IC3, and IC3's internal state goes high. The latching pulse at LE forces IC3's DATA_OUT high, again following the state of DATA_IN.

IC1, IC2, and IC3 operate from a single 5V power supply. Separate bypass capacitors placed adjacent to each device's power pins minimize noise. Resistors R3 and R4 set IC3's trigger-voltage threshold. Transformer T1 provides a 1-to-1-to-1 turns ratio and comprises a single-hole ferrite bead (Fair-Rite part number 2673000101) with three identical single-turn windings. To minimize stray inductance, keep the connection to the junction of windings W1, W2, and IC1 as short as possible. Also, the grounded end of W2 should return to IC1's ground connection.

The circuit's isolation capabilities depend on its pc-board layout and the properties of transformer T1, whose type 73 ferrite core is moderately conductive. Thus, T1's isolation properties depend on its windings' insulation. For example, Teflon or Kapton-insulated wire can withstand several kilovolts. If you carefully construct T1 using the specified core and Teflon-insulated AWG #24 wire, the transformer can exhibit interwinding capacitances of 0.2 pF or less.

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