Circuit provides ISFET-sensor bias
ISFETs (ion-sensitive field-effect transistors) are useful for measuring the acidity of fluids. Accurate measurements require that the ISFET's bias conditions (ID and VDS) be held constant while the gate is exposed to the fluid under test. The acidity of the fluid changes the channel width, resulting in a gate-source voltage, VGS, that is proportional to the fluid's pH. A recently published Design Idea shows a biasing circuit for the ISFET (Reference 1). The circuit in Figure 1 provides a simpler and more accurate implementation. Voltage VA sets ID, the drain current, through ISFET Q1, while voltage VB sets VDS, the drain-source voltage across Q1. Both AD8821 high-precision instrumentation amplifiers, IC1 and IC2, are configured for unity gain. IC3, the AD8627 precision JFET-input amplifier, buffers the drain voltage, VD, ensuring that all of the current flowing through R1 flows through Q1.
To control ID, amplifier IC1 forces the differential voltage between its output and the reference input to equal its differential input voltage, VA. Because the sensed differential voltage is equal to the voltage across R1, ID=VA/R1. With R1 set to 20 kΩ, ID scales to 50 µA/V. Similarly, amplifier IC2 forces the differential voltage between its output and the reference input to equal its differential input voltage, VB, thus forcing VDS to equal VB. (Note: If your design does not require independent adjustment of VDS and ID, the circuit can operate from a single control voltage. Tie VA and VB together and drive it with the desired voltage VDS. R1 is then equal to VDS/ID.) The voltage of interest, VGS, appears between the gate voltage and the output of IC2. A useful feature of this circuit is that the current source floats, enabling the gate voltage to connect to any voltage within the common-mode range of the circuit. For this circuit, the range of VG is (VA+2–VEE)G&(VCC–2–VA).
Figure 2 shows the advantage of the floating gate when the circuit is connected to the AD7790 differential-input sigma-delta ADC. The gate voltage connects directly to the ADC's reference. The only signal-conditioning circuitry required between VS or VG and the ADC's input is a simple RC filter. The 0.1% error in resistor R1 dominates the current-source errors for currents higher than 1 µA and, therefore, are less than 250 nA for drain currents as high as 250 µA. The VDS errors originate from the gain error of IC3 and input offset voltages of IC2 and IC3. The error in drain-source voltage is less than 450 µV for drain-source voltage as high as 2V.
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