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Positive feedback yields fast amplifier with precision dc offset

-April 01, 2004

Some signal-processing applications require a high-speed, low-noise, dc-coupled amplifier that incorporates a precision dc-offset adjustment. Examples include oscilloscopes, in which the offset adjustment typically acts as a "position" control), ADC-input gain blocks, and scanning-ion-beam-microscopy deflection circuitry. Figure 1 illustrates the circuit concepts. Op amp IC2A is a 70-MHz, high-slew-rate device configured with a fixed gain of 3 (9.5 dB) and a ±10V precision offset adjustment. Op amp IC1A buffers and thereby linearizes the offset potentiometer. IC1A is a low-cost, low-frequency device that befits the dc circuit it occupies. But the mismatch between the frequency responses of IC2 and IC1A creates the need for the novel topology of Figure 1. An obvious way to couple IC1A and IC2A, which might seem to allow the addition of dc offset, would be to omit R1, R2, R5, and C1 and simply connect IC1A as a unity-gain buffer providing the termination for the gain-set resistor, R3. Unfortunately, this scheme wouldn't work, because the output impedance of the pokey IC1A starts rising at frequencies far below the capabilities of the speedy IC2.

This drawback would ruin the high-frequency performance of the composite amplifier. You could (partially) avoid this problem by using another LM1364 in place of the LM324, but the result would be a significantly noisier circuit because of the summation of IC1A's output noise with the signal at point V2. This Design Idea offers a different approach, in which C1 provides a robust, low-impedance termination for R3, and the R2C2 time constant isolates the signal path from noise originating in either IC1A or the VR1 and VR2 voltage references. Unfortunately, this approach creates a problem arising from R2's dc resistance. C1 holds down the bottom end of R3 for ac-signal frequencies higher than 1 kHz or so. But near dc, R2 and R3 tend to sum, and the summing action would make the closed-loop gain of IC2 approximately 10% less for dc-signal components than for ac. The circuit avoids this effect by using positive feedback that R1 and R5 provide.

The dc gain that R1 and R5 provide generates a compensation-voltage component that nulls the voltage drop across R2. This action cancels the tendency of the R3C1 node to track IC2A's input and makes IC2's output accurately equal to VOUT=V2(1+R4/R3)–V3(R4/R3)=3V2+2V3. The rest of the schematic illustrates the use of the offset circuit in a dual-channel amplifier. In this amplifier, the variable-gain front ends incorporate a pseudologarithmic gain adjustment spanning gains of 0.5 to 10 (–6 to +20 dB). To achieve this wide gain-control range with a single-turn potentiometer and maintain reasonable adjustment resolution without compromising the LT1364s' 20-MHz capability, the control potentiometer, R7, is connected such that its resistance element serves two circuit functions. The left half forms a variable-gain (1 to 3.33=0 to 10.5 dB) feedback network around IC2A. The right half forms a variable-loss (1 to 0.167=0 to –15.5 dB) circuit. The net result, when you combine it with the fixed 9.5-dB gain of IC2A, is an overall gain variable from (0–15.5+9.5)=–6 dB when you adjust R7 to one extreme to (10.5–0+9.5)=20 dB when you adjust R7 to the other extreme. IC1C finishes the gain-block subsystem by generating tracking ±12V rails, by splitting the ground of the 7824 24V regulator. This regulator uses as its source an inexpensive, unregulated wall-socket power supply.

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