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Add an auxiliary voltage to a buck regulator

-October 31, 2002



You often need more than one regulated output voltage in a system. A frequently used and reasonably simple way to create this auxiliary output voltage is to add a second winding to the output inductor, creating a coupled inductor or a transformer, followed by a diode to rectify (peak-detect) this output voltage. The biggest drawback of this approach is that the diode's voltage drop varies with temperature and load current and can have a 2-to-1 variation, resulting in poor output-voltage regulation. This problem be-comes more critical as output voltages decrease and may require the addition of a linear regulator. The circuit shown in

Figure 1

is an alternative approach that replaces this diode with Q2, a p-channel FET. The circuit works as follows:

During the conduction time of FET Q1, the voltage across the primary winding of transformer T1 clamps to the voltage, VOUT+VF1, where VF1 is the voltage drop across FET Q1. Through transformer action, the voltage on the secondary winding of inductor L1 is equal to the turns ratio between the windings times the voltage across the primary winding. The output capacitor on the auxiliary output, V02, then charges to the peak of the secondary-winding voltage. FET Q2 turns off when Q3 turns back on to prevent the output capacitor from discharging. The secondary voltage floats; you can add it to the main output voltage by tying one end of the secondary winding to the main output. You can also tie it to ground for an output voltage lower than V01, if desired. The equation that defines the auxiliary-output voltage for the circuit in

Figure 1

is:

The second half of this equation represents a voltage-error term between FETs Q1 and Q2. To cancel out the error attributable to the FET voltage drops, you need to make the voltage drop of FET Q2 equal to VF2=VF1×(NS/NP), where NS/NP is the transformer's turns ratio. Because these FET voltages are a function of the output currents and the on-resistance of the FETs, you can select the on-resistance of FET Q2 by using the following equation:

In Figure 2, the main output voltage is 3.3V, yielding an inductor primary voltage when Q1 is conducting equal to only 3.44V, because of the low voltage drop across FET Q1. Thus, if you wanted a 5V output, the secondary winding would need to develop an additional 1.7V, necessitating a 2-to-1 step-down turns ratio. The desired on-resistance of the FET internal to IC1 from the above equation should be 0.16Ω to cancel the voltage drop across Q1 at maximum loads and while operating from a 5V input voltage. This example uses a 0.20Ω FET with a voltage drop equal to only 88 mV. This choice allows for good voltage matching between FETs Q1 and the FET internal to IC1, resulting in excellent error cancellation, less power loss, and better overall output-voltage regulation than diode rectification provide. An added benefit of this approach is that you can use it with controllers that have integrated switching FETs, because you don't need access to Q1 and Q3 gate drives. Measured results, although varying both outputs' loads over their full operational range, showed less than a ±3% variation in the 5V output.

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