Circuit sequences supplies for FPGAs

-January 23, 2003

System designers must consider the timing and voltage differences between core and I/O power supplies (in other words, power-supply sequencing) during power-up and power-down. The possibility of a latch-up failure or excessive current draw exists when power-supply sequencing does not occur properly. The trigger for latch-up may occur if power supplies apply different potentials to the core and the I/O interfaces. FPGAs and other components with different sequencing requirements further complicate the power-system design. To eliminate the sequencing problem, you should minimize the voltage difference between the core and the I/O supplies during power-up and -down. The power supply in Figure 1 regulates the 3.3V input voltage to the 1.8V core voltage and tracks the 3.3V I/O during power-up and -down to minimize the voltage differences between the supply rails.

The circuit in Figure 1 comprises IC1 and IC2, a TPS2034 power switch and a TPS54680 step-down switching regulator, respectively. Component IC1 is a high-side power switch that generates a slow ramp that IC2 tracks during start-up. The ramp time of 6 msec minimizes the inrush currents to the bulk capacitors on the power-switch and supply outputs. The slow ramp minimizes the transient-current draw of the FPGA. The power switch ensures that the I/O voltage is not applied to the load before IC2 has enough bias voltage to operate and generate the core voltage. Assuming that the input supply voltage is at 3.3V on J1, floating the J2 connector enables component IC1. The I/O supply voltage, J3, slowly rises until it reaches 3.3V. As the I/O voltage rises, the core voltage supply, J4, rises accordingly until the voltage reaches 1.8V (Figure 2). The TPS54680 device incorporates an analog multiplexer on the TRACKIN pin to implement the tracking function.

During power-up and -down, when the voltage on the TRACKIN pin is lower than the internal reference of 0.891V, the voltage on the TRACKIN pin connects to the noninverting node of the error amplifier. When the TRACKIN pin is below 0.891V, the pin effectively functions as the switching regulator's reference. The resistor divider of R3 and R4 on the TRACKIN pin must equal the resistor divider of R1 and R2 in the feedback compensation to track with minimal voltage difference during power-up and -down. The TPS2034 has an on-resistance of 37 mΩ and can supply as much as 2A output current. The TPS54680 is a synchronous buck regulator that contains two 30-mΩ MOSFETs. Because the TPS54680 can source and sink as much as 6A load current at efficiencies greater than 90%, the output can track another power-supply rail during power-down. When the IC1 device becomes disabled by shorting J2 to ground, the I/O supply voltage decays, and the core supply voltage follows once the I/O voltage falls below the core voltage (Figure 3). Typically, Schottky diodes connect to the output of a dual power supply to clamp the voltage difference between the core and the I/O supplies during power-down, but most applications do not require the diodes with the power-supply circuit in Figure 1. Using this power-supply design reduces component count and increases reliability by eliminating the potential for latch-up and reducing FPGA start-up transient currents.

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