EDN Access -- 05.26.94 Pulse generator verifies test setup
Design Ideas: May 26, 1994
[Editor's note: The image links below don't work; here's a scan of the print article –MD]
Verifying the rise-time limit of wideband test-equipment setups is a difficult task. In particular, you must often know the "end-to-end" rise time of an oscilloscope/probe combination to ensure measurement integrity. Fig 1's circuit provides an 800-psec pulse having rise and fall times shorter than 250 psec. The pulse's amplitude is 10V, and the circuit's source impedance is 50 Ohm. The circuit is similar to the one Ref 1 details, except that this circuit is triggerable instead of free-running. This triggering feature permits synchronizing with a clock or another event. You can vary the delay of the output with respect to the trigger by 200 psec to 5 nsec.
The circuit requires a high-voltage bias for operation. A cascoded high-voltage transistor, Q2, combines with a switching regulator IC1 to form a high-voltage, switched-mode supply. IC1 pulse-width-modulates Q2 at a 100-kHz clock rate. L1's inductive events get rectified and stored in the 2-mF output capacitor. The adjustable resistor divider provides feedback to IC1. The diode and RC combination at Q2's base damp inductor-related parasitic behavior. The 10-k Ohm/1-µF pair filters noise from the supply line.
The R3/C1 combination applies high voltage to Q1, a 40V-breakdown device. Set the high-voltage "bias-adjust" control at the point where free-running pulses across R4 just disappear. This setting puts Q1 slightly below its avalanche point.Subsequently, applying an input trigger pulse causes Q1 to avalanche. The result is a quickly rising, very fast pulse across R4. C1 discharges, Q1's collector voltage falls, and breakdown ceases. C1 then recharges to just below the avalanche point. At the next trigger pulse, this sequence repeats.
Fig 2 shows the circuit's waveforms. The input trigger pulse is Trace A. Its amplitude provides a convenient way to vary the delay time between the trigger and output pulses. A 1 to 5V setting range produces a continuous 5-nsec to 200-psec delay range.
The circuit requires some special considerations for optimal performance. L2's very small inductance combines with C2 to slightly retard the trigger pulse's rise time. This retardation prevents significant trigger-pulse artifacts from appearing at the circuit's output. You should select C2 for the best compromise between output-pulse rise time and waveform purity. You may also have to select Q1 to get the desired avalanche behavior. Such behavior, while characteristic of the device, is not guaranteed.
A sample of 50 Motorola 2N2369s, spread over a 12-year date-code span, yielded 82% usable devices. All "good" devices switched in less than 600 psec. Select C1 for a 10V output amplitude. C1 is typically between 2 and 4 pF. Ground-plane construction with high-speed layout, connection, and termination techniques are essential for good results from this circuit. (DI #1427)
EDN Magazine. EDN is a registered trademark of Reed Properties Inc, used under license.