Switched-capacitor IC controls feedback loop

-February 17, 2000

You can implement a simple control loop with a constant setpoint over a wide range of control by using a switched-capacitor filter. The circuit controls motor speed over 1 to 200 Hz or 60 to 12,000 rpm. In Figure 1, a National LMF40CIWM four-pole lowpass filter is the heart of the design. This filter has a cutoff frequency defined by the clock divided by 50. Consider this filter as a difference amplifier that compares the difference between two frequencies. The relationship between the clock divided by 50 and the 500-count encoder divided by 2 is such that when the clock rate is 1000 times the revolutions per second of the motor, the signal frequency from the encoder is at approximately the midpoint of the filter response. This midpoint is the point of zero error and is approximately 2V p-p. The rectified output serves as the dc setpoint voltage for the control loop. If the motor speed increases, the voltage decreases, and if the motor slows down, the voltage increases. As simple as the method is, it can drive a motor-control chip and provide good speed regulation.

You can use the method to control other servo loops that provide a feedback frequency within the range of the filter. The big advantage of this scheme is that the setpoint remains constant with a range of speed settings. Another advantage is that the clock provides direct speed calibration thanks to the 1000-to-1 relationship between the clock and the rotational speed of the motor. Figure 2 shows some circuit details for enhanced operation. To cover the higher speed range, you need an additional divide by 10 to stay within the frequency range of the filter. An example is given for 6- and 60-Hz rotational speeds. Conventional op-amp circuits buffer and rectify the output of the filter. The application uses one of many full-wave op-amp-rectifier circuits that follow a buffer with a gain of 2. After rectification, the 75-kW resistors and 0.1-µF capacitor provide some filtering and time-constant conditioning. You set the gain of op amp 1 so its output dc voltage is 2.5V at the operating point. Op amp 2 offsets this voltage and moves the operating point to 0V when no speed error is present. The offset-adjust trimmer allows for minor variations and calibrates the actual rotational speed to the clock signal. Op amp 3 provides gain for the proportional signal.

You can use a fixed resistor in place of the 200-kW trimmer. Op amp 4 is an integrator circuit that provides the classical integral control for the loop. The integrator makes up for errors in the following control circuits and motor characteristics throughout the control range. The integrator control-point output voltage therefore changes at different speed settings. Buffer op amp 5 sums the proportional and integral signals at its input. A clamp diode limits the positive drive voltage and prevents any negative excursions from driving the loop to a latch-up condition. In an application, the clamping limits the output to 4.3A, because the motor-control circuit has a drive characteristic of 1A per volt. When the motor stops, the FET stop switch clamps the control signal to zero. Additional circuits control acceleration rate, braking rate, and direction. The speed accuracy for the system is a nominal 0.002% throughout the range. The speed clock comes from a DDS chip, and all the above functions are under control of a PC or front-panel switch settings. (DI #2486)

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