You can implement a simple and low-cost keyboard encoder by using a key-controlled resistive divider connected to an ADC (Figure 1). This type of circuit is especially suitable for embedded systems that use a µC with an integrated ADC section. To obtain the best noise margin between keys, select resistors to yield an equal division of the voltage levels. To meet this criterion using the circuit in Figure 1, you must use a set of resistors with all-different, specific values. For example, a 10-key keyboard uses a 10-k pullup resistor, RP, and values of 1.1, 1.3, 1.8, 2.4, 3.3, 5.1, 8.2, 16, and 51 k for R1 through R9 . Using commonly available resistor values and tolerances and taking account of the key resistivity and ADC linearity errors, you're limited in the number of keys you can encode with a safe noise margin. Using an 8-bit ADC, the cited 10-key example is close to that limit.
The circuit in Figure 2, despite its many resistors, overcomes the problem of the many restore values. The circuit is symmetric and uses the same two resistor values for all keys. It is also easy to expand the circuit for more keys. As in Figure 1's circuit, if you simultaneously press more than one key, the circuit detects only the key whose connection is closest to the ADC. The chain of R1 resistors defines the voltage level associated with each key. Their nominal value is a trade-off between the power dissipation and the values of R2 and R3, which depend on R1; the total number of keys; and the desired noise margin. R2 minimizes the voltage deviations at the nodes of the R1 chain whenever you simultaneously press two or more keys. Therefore, you should calculate its value, much higher than that of R1, by taking into account R1 and the desired width of the voltage window associated with each key. Similarly, R3's value should be much higher than that of R2 to ensure that the voltage level associated with each key almost completely transfers to the ADC's input.
The circuit was tested by encoding 15 keys with one 8-bit analog input of the Microchip PIC16C71 µC. The resistor values are 47, 3.9 k, and 4.7 M for R1, R2, and R3, respectively. Only R1 needs a tight tolerance; the others are less demanding. The window of key acceptance is set to a 7-LSB interval centered on the theoretical key level. This interval is large enough to accommodate the worst case (simultaneously pressing the two more-distant keys from the analog input) with a safety noise margin between valid keys of 10 LSBs. (DI #2319).
RS-232C circuit has galvanic isolationIoan Ciascai, REI Data, Napoca, Romania
You can obtain longer transmission distances with the RS-232C interface if you use galvanic isolation between the two linked terminals. Galvanic isolation also eliminates problems arising from disparate potentials between terminals. Using two MAX860/861 ICs and two TPL2200 optoisolators, you can obtain galvanic isolation for three-wire transmission without external supplies (Figure 1). The MAX860/861 circuits, which generate two voltages of different polarity, regardless of the polarity of TxD, which provides the supply voltage, are the basis of the design.
For the positive TxD polarity, the MAX860/861 ICs function as voltage inverters, whereas for negative-polarity TxD, the ICs function as voltage doublers. Diodes D1 and D7 provide the positive supply voltages; D4 and D9 provide the negative supply voltages, depending on the polarity of TxD. The diode-resistor pairs D5, R1 and D10, R2 determine the operating mode (doubler or inverter) of the MAX860/861 ICs, depending on the polarity of TxD. Zener diodes D2, D3, D6, and D8 protect the MAX860/861 ICs from supply overvoltages.
The digital-output TLP2200 optoisolators provide galvanic isolation and generate the RxD received signals with RS-232C logic levels. The circuit provides galvanically isolated communication in full-duplex mode at any standard transmission speed. The use of galvanic isolation allows transmission over nearly twice the distance for nonisolated systems. If you use a four-wire cable and split the separation circuits at the cable ends, you can further increase the transmission distance. (DI #2315).
Digital pot adjusts LCD's contrastJef Collin, CSE Systems, Turnhout, Belgium
You can use a digitally controlled potentiometer for many purposes. In this example, you can use the device to regulate the contrast of a standard (such as two lines by 40 characters) LCD. You can use the circuit in Figure 1 in a portable test system, in which you need to change the contrast of the LCD as a function of the viewing angle. You choose the contrast setup from a menu and then use up or down buttons with µC IC1 to adjust the contrast. The µC stores the contrast value in the digital potentiometer, IC2. This design uses a Xicor 10-k unit (dubbed "EEPOT"), but you could use other devices in the design.
The EEPOT connects to the LCD's VO line. You could connect the other side of the potentiometer to ground, but, for better contrast, you can apply a negative voltage to this terminal. This circuit has a serial interface, so it uses the negative-voltage generator in the MAX232 RS-232C/TTL converter. Listing 1 is the subroutine for the 8051 µC. The program calls the routines for contrast-up or -down. (DI #2314).
Add speech encoding/decoding to your designRodger Richey, Microchip Technology Inc, Chandler, AZ
Adding speech capabilities to a design can sometimes lead to complex algorithms and expensive DSPs or specialized audio chips. However, with the completion of a simplified adaptive differential pulse-code-modulation (ADPCM) algorithm, you can now implement these audio capabilities in low-cost 8-bit µCs, which typically have lower power consumption and cost than their DSP or audio-chip counterparts. A two-chip design is feasible by offloading the encoding and decoding tasks onto the µC as if it were a peripheral.
Since 1991, the Interactive Multimedia Association (IMA) Digital Audio Technical Working Group (DATWG) has been working to define a cross-platform digital-audio exchange format. An inherent problem exists with the exchange of audio data between PC, Mac, and workstation computers. Each computer has its own data types and sampling rates. In May 1992, IMA DATWG published the first revision of the Cross-Platform Digital Audio Interchange recommendation that specifies three uncompressed and one compressed data type at various sample rates. The compressed data type is the Intel (www.intel.com) 4-bit DVI ADPCM algorithm. This algorithm compresses a 16-bit signed audio sample into 4 bits and takes advantage of the high correlation between consecutive samples, which enables the prediction of future samples. Instead of encoding the sample itself, ADPCM encodes the difference between a predicted sample and the actual sample. This method provides more efficient compression with fewer bits per sample and yet preserves the overall quality of the audio signal. Both the encoder routine (Listing 1) and the decoder routine (Listing 2) are written in C to ease readability.
The hardware implementation depends on the type of interface. With a parallel interface, you can use the PIC16C556A (Microchip Technology, www.microchip.com) (Figure 1a). A standard parallel interface uses the chip-select (CS), output-enable (OE), and write-enable (WR) pins on Port A. The 8-bit data interface connects to the 8-bit Port B on the µC. You can use two additional I/O lines for status information, such as encode/decode select, to the µC or an interrupt line to the main controller to indicate when data is ready. CS, which connects to the RA4 pin, can interrupt the PIC16C556A on the start of a transmission.
The second hardware implementation uses a serial interface and an eight-pin µC (Figure 1b). The PIC12C672 uses four of the pins for power, ground, and oscillator input and output. Three of the remaining I/O pins are for clock (SCK), data in/out (DIN/DOUT), and CS. You can use the other I/O pin to indicate the desired encode/decode operation or as an interrupt to the main controller. CS connects to the external interrupt pin, GP2, to detect the start of a transmission.
Both µCs have a flexible oscillator structure for use with a crystal, a resonator, or an external clock signal. Both parts of the figure show the µC using an external crystal as the clock source. Because these devices are fully static, the main controller can provide the clock source to the µC. By turning the clock source on and off as necessary, the main controller can further decrease overall power consumption. This method also allows control of the speed at which the algorithm runs, which is proportional to the sample rate of the system.
To fully implement the µC as an ADPCM-encoder/decoder peripheral requires firmware to implement the serial or parallel interface, such as listings 1and 2, and a main routine to tie everything together. The main controller is responsible for sampling the incoming audio waveform, storing and retrieving the ADPCM codes from nonvolatile memory, and then playing the resulting samples. The main controller feeds samples or ADPCM codes to the µC and then reads the resulting ADPCM codes or samples from the µC.
Cheap PWM IC makes synchronous gate driverDimitry Goder, Switch Power Inc, Campbell, CA
A system with a µP, memory, and peripherals usually requires several power-supply voltages. Designers typically use local switching regulators to produce the desired voltage rails. One of the most common topologies, the synchronous buck regulator, converts a 5 or 12V bus to some other, lower voltage. This approach has gained vast acceptance, thanks to its relative simplicity and high conversion efficiency. Specialized synchronous buck controllers are available, but you generally pay a premium for these ICs. Meanwhile, many inexpensive, general-purpose PWM controllers are available, but they require you to implement synchronous rectification with discrete circuitry. The implementation is a difficult task, because it involves building two out-of-phase, mutually exclusive gate drivers. The block diagram in Figure 1 shows how to use any general-purpose PWM controller (for example, the CS3843 from Cherry Semiconductor in East Greenwich, RI) to configure a synchronous buck regulator.
The most critical aspect of the driver design is nonoverlap timing, which prevents simultaneous high states at gates H and L, thus eliminating the simultaneous turn-on of Q1 and Q2, with resulting shoot-through currents. Figure 2 shows details of the driver block. The input signal passes through two inverters, IC1A and IC1B, to generate the Gate H signal in phase with the input. The complementary follower, Q1 and Q2, forms a current amplifier to provide sufficient drive for the top MOSFET. Meanwhile, IC1D inverts the input, and Q3 and Q4 amplify the signal to drive the bottom MOSFET.
IC1C and IC1E provide the nonoverlap function. Each of the inverters ensures a low state at the corresponding gate-drive output until the other driver's output falls below a certain threshold. This function prevents simultaneous high states, regardless of the circuit delays and the type of MOSFETs you use. The TTL switching threshold and the values of R1, R2 and R3, R4 determine the nonoverlap threshold. The threshold is approximately 3V for the circuit in Figure 2, but you can easily adjust it for other values.
Creating a high-side driver requires a bias voltage higher than the input voltage. A 12V line is commonly available, so you can use it to power the driver. The outputs of IC1B and IC1D must swing between ground and 12V; you thus need a 7406 open-collector inverter with a high-voltage capability. If 12V is unavailable, you can use charge-pump circuitry to double the input voltage. The driver shows excellent performance, with 60-nsec nonoverlap time, superior to that of many available ICs. Figure 3 shows the two gate drivers' outputs, with each driver switching an IRL3103 n-channel MOSFET, a good choice for a 10A converter. The total cost of the driver does not exceed 30 cents. (DI #2306).
Circuit detects total on-timeRichard Nachazel, Vista Electronics Co, Ramona, CA
The circuit in Figure 1 provides a voltage that is directly proportional to the sum of the total on-times for a number of positive pulses that occur during the interval between sample signals. When a positive pulse arrives at the control input to switch IC1A, a constant-current source charges capacitor C1 through IC1A for the duration of that pulse and for each subsequent pulse. The constant-current source comprises Q1; R1; C1; and R2, which drives Q1's gate at C1's potential. C1 and C2 should be noninductive and have low dielectric absorption.
When you apply a low signal to the Sample line, the sample/hold circuit (IC2) latches the analog voltage on C1. You adjust R4 for 0V at the output with no pulses at the input. The trailing edge of the Sample signal switches IC1B on, discharging C1 to an initial 0V potential. You can connect unused analog switches in parallel with IC1B to speed the discharge. Higher supply voltages also improve the circuit's speed and performance. (DI #2300).