CMOS circuit latches relays
The differential-pulse converter comprises IC1C, IC1D, IC1E, and IC1F. The last two stages of the CD4069 hex inverter are self-biased in linear mode around VDD/2, where VDD is the drain-to-drain voltage and corresponds to Pin 14 of IC1. The circuit takes a rise or a fall at IC1C and converts it to opposing pulses of equal length at the outputs of IC1E and IC1F. The order of the pulses is synchronous with the edge direction at the input of IC1C.
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Assuming that the circuit powers up with C1 uncharged, IC1A and IC1B always start off in a state in which R1 sees VDD on both sides. All inverter stages operate in digital mode except for IC1E and IC1F.
When you apply power to the circuit, these two stages self-bias around VDD/2 and operate in linear mode. The op amps, wired as followers, also bias their outputs near VDD/2. That action leaves the relay coil with a negligible offset/error voltage thanks to the matching of the devices in the hex-inverter IC and the op amps’ high open-loop gain.
R3/C3 and R4/C4 establish time constants, which roughly set the total length of these pulse tails at 500 msec. This time is more than enough to satisfy the relay coil’s hold requirements, which, for the Panasonic TQ2-L-5V, are 3 msec or less. If the relay coil at first finds itself in an asynchronous position, it can reorient itself after a single push of the switch if necessary.
Dropping IC1’s VDD through series-supply resistor R5 limits the idling currents in linear-biased stages IC1E and IC1F. This resistor represents a compromise between the power these two stages dissipate and the available voltage swing to toggle the relay through the op amps.
The circuit operates from a 9V source, and, with the component values in Figure 1, IC1’s VDD lies at approximately 5.5V. The overall current draw between toggles is approximately 8 mA.