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Circuit simultaneously delivers square and square root of two input voltages

Marián Štofka, Slovak University of Technology, Bratislava, Slovakia -March 01, 2012

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This Design Idea requires inputs from the circuit in a previous Design Idea (Reference 1). IC1 and IC3 are ADG5213 quad switches with individual logic-level control inputs (Figure 1 and Reference 2). With a high input, switches S2 and S3 are open, and switches S1 and S4 are closed. The switches toggle to opposite states with their control inputs low. The circuit is in the idle pretriggered condition. During the initial idle condition before a clock rising-edge trigger, Q is high and, through IC8, holds switches S2 and S3 of IC1 in the open position.

Circuit simultaneously delivers square and square root of two input voltages figure 1

Q overbar is low, and, through IC7’s Reset high closes IC1’s S1 and S4, discharging CT2 and CT4 and zeroing the input voltage to unity-gain amplifiers IC2D and IC2C. Q overbar low also sets Track 2 low through IC6 and holds IC3’s S1 and S4 in the open position. The circuit retains any sampled voltages from a previous operation in sample-and-hold capacitors CS1 and CS2; these voltages appear at VOUTX and VOUTY through unity-gain amplifiers IC2A and IC2B.

Signals VOUTL and VOUTQ from the linear and quadratic pulse generator are at 0V during idle, holding comparator outputs IC4 and IC5 low. A rising trigger edge at the clock signal begins the ramp generation of VOUTL and VOUTQ. The Q and IC8 outputs fall low, closing IC1’s S2 and S3 and ensuring that Track 2 remains low. Q overbar rises and forces Reset low through IC7, opening S1 and S4 of IC1 and allowing CT2 to follow the rising VOUTQ and CT4 to follow the rising VOUTL.

When linear ramp VOUTL rises to analog input VX, IC4’s output rises and, through IC8, Track 1L opens S2 of IC1 and allows CT2 to hold the present level of VOUTQ. In a similar manner, when quadratic ramp VOUTQ rises to analog input VY, IC5’s output rises and, through IC8, Track 1Q opens IC1’s S3 and allows CT4 to hold VOUTL’s present level. The pulse generator terminates when the ramps reach 5V. The ramps then fall back to 0V, Q returns high, and Q overbar returns low.

The fall of Q overbar triggers IC7 to produce a 50-μsec delayed rise on Reset, which RD2 and CD2 time to occur after Track 2 has returned low and the sampled voltages are safely captured on CS1 and CS2. Reset’s high state closes IC1’s S1 and S4, discharging CT2 and CT4 in preparation for the next trigger. VOUTX is the squared voltage of input VX, and VOUTY is the square root of the voltage of input VY.

Operation of the circuit is illustrated in Figure 1. For the sake of simplicity, both analog input voltages VX and VY have a value of (3/5)VPEAK; VPEAK represents here a full-scale of both input voltages. The VX, which is compared by IC4 comparator with the linear sawtooth pulse VOUTL produces therefore a pulse width of Circuit simultaneously delivers square and square root of two input voltages equation 6. Subsequently, the trailing edge of the latter pulse width stops tracking of the quadratic sawtooth voltage VOUTQ at the level of Circuit simultaneously delivers square and square root of two input voltages equation 5.

Circuit simultaneously delivers square and square root of two input voltages figure 2

Contrarily, VY is compared in IC5 comparator with the quadratic VOUTQ reference pulse and the resulting pulse width at output of COMPQ has a value of  Circuit simultaneously delivers square and square root of two input voltages equation 3. Trailing edge of this pulse stops tracking of linear VOUTL time-base at the level of  Circuit simultaneously delivers square and square root of two input voltages equation 4. If you normalize both output voltages by VPEAK, you get numbers of Circuit simultaneously delivers square and square root of two input voltages equation 1 and Circuit simultaneously delivers square and square root of two input voltages equation 2, and these correspond to square and square root of the input of "3/5".

Circuit simultaneously delivers square and square root of two input voltages figure 3

Note that the described circuit is flexible with its further possibilities to create other mathematical functions. If you need fourth power of input voltage, Circuit simultaneously delivers square and square root of two input voltages equation 7, you connect output of X channel to input of Y channel; while you slightly rearrange the COMPQ comparator IC5 by disconnecting its positive input and connecting it to positive input of the COMPL comparator IC4. At output of Y channel you get the desired function of Circuit simultaneously delivers square and square root of two input voltages equation 7. In other words, you made this way a cascade of two identical squaring channels.

Similarly you can connect a cascade of two identical square-rooting channels, which offers you fourth-root function, Circuit simultaneously delivers square and square root of two input voltages equation 8 at output of X channel.

Editor's note: The figures were updated on March 4, 2012.

References
  1. Štofka, Marián, “Positive edges trigger parabolic timebase generator,” EDN, July 28, 2011, pg 51.
  2. ADG5212/ADG5213 High Voltage Latch-up Proof, Quad SPST Switches,” Analog Devices, 2011.

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