Survival guide to high-speed A/D converter digital outputs part 2

Jonathan Harris -July 03, 2012

In the analog to digital converter (ADC) space today there are primarily three types of digital outputs employed by ADC manufacturers.  As was discussed in Part I of this article, “Survival Guide to High Speed A/D Converter Digital Outputs”, these three outputs are Complementary Metal Oxide Semiconductor (CMOS), Low Voltage Differential Signaling (LVDS), and Current Mode Logic (CML). 

Each type was presented and discussed in terms of how they operate and how they are typically employed in ADC designs based on sampling rate, resolution, output data rates, and power consumption requirements.  In this subsequent article, the implementations of these interfaces will be discussed. 

The practical applications of each of these three types of outputs will be presented along with things to look out for when selecting and using these different outputs.  General guidelines for how to deal with each of these outputs will also be presented as well as a discussion of the advantages and disadvantages of each of output.

The Basics

There are some common rules and things to consider when working with digital interfaces regardless of the type of digital output.  First, for the best terminations, it is best to use real resistor terminations at the receiver (FPGA or ASIC).  Reflections seen at the receiver can possibly break the timing budget in the system.  When dealing with CMOS and LVDS outputs do not use the DCO (Data Clock Output) from one ADC if using multiple ADCs in a system.  This can lead to timing errors and improper data capture at the receiver.  This is especially important in I/Q systems where accurate timing between two ADCs is necessary. 

Even in this case where the two ADCs are typically in the same package, it is important to utilize the appropriate DCO output for each ADC.  This ensures that accurate timing relationships can be maintained.  Another important parameter to remember is the data format. 

It is important to make sure the ADC and the receiver are aligned to the same data format (i.e. 2’s complement or offset binary).  In addition to these items, the speed of data transfer is important.  As the data rates increase, the distance at which the data can be properly captured at the receiver decreases.  This is due to interconnect and cable bandwidth limitations and resulting issues such as inter-symbol interference. These are just a few reasons why it is important to consider the interconnect as transmission lines. 

It is important to treat the interconnect in this manner and understand the characteristics of transmission lines.  It becomes even more important as the data rates increase to understand the interconnect in this manner.  Care must be taken to ensure correct conductor dimensions as well as proper spacing distance between the signal and return layers.  It is also important to select a board material with constant dielectric properties so that trace characteristics fluctuate as little as possible across the length of the interconnect. 

Ideally, transmission lines would propagate to infinity; however, in real implementations this is obviously not possible.  The results are things like skin effect, dielectric loss, and radiation loss which all influence the transmission line parameters and degrade the signal.  This is why it is important to properly design the transmission lines with the right physical parameters and also ensure matching impedances between the transmitter and the receiver.  Doing so will conserve energy and get the maximum signal possible delivered to the receiver.

CMOS – What you need to know

There are several things to consider when looking at CMOS outputs.  First, consider the typical switching speed of the logic levels (~1 V/ns), output loading (~10pF/gate driven) and charging currents (~10mA/output).  It is important to minimize the charging current by using the smallest capacitive load possible.  This is done by driving only one gate with the shortest possible trace without vias where possible.  In addition, a damping resistor can be used to minimize the charging current as illustrated in Figure 1. 

It is important to minimize these currents because of how quickly they can add up.  For example, a quad channel 14 bit ADC could have a transient current as high as 14 x 4 x 10 mA which would be 560 mA!!  The series damping resistors will help suppress this large transient current.  This will help reduce the noise generated by the transients in the outputs and thus, help prevent the outputs from generating additional noise and distortion in the ADC.

Figure 1. CMOS Output Driver with Damping Resistor

The time constant of the damping resistor and the capacitive load should be less than approximately ten percent of the period of the output data rate.  For example, if using an ADC with a sample rate of 80 MSPS and capacitive loading of 10 pF on each of the CMOS outputs, the time constant should be approximately ten percent of 12.5 ns which would be 1.25 ns.  Thus the damping resistor, R, can be set to 100 ohms, a value that is readily available and meets the time constant criteria. 

Choosing R values larger than ten percent of the period can degrade output data settling time and interfere with proper data capture at the receiver.  The capacitive loading on the CMOS outputs from the ADC should be limited to a single gate load and under no circumstances be connected directly to a noise data bus.  To connect to a data bus, an intermediate buffer register should be used to minimize the loading of the CMOS outputs from the ADC. 

As the data rate increases on the CMOS outputs, the transient currents also increase and result in higher power consumption.  Figure 2 illustrates the different power consumption requirements of CMOS, LVDS, and CML outputs for a dual 14-bit ADC.  At approximately 150 – 200 MSPS and 14 bits of resolution, CML output drivers start to become more efficient in terms of power consumption.  Unlike CMOS outputs, CML and LVDS outputs operate in such a manner that their power consumption stays relatively constant. As the data rate increases, the power consumption of the CMOS outputs track almost linearly.  This increased power consumption is compounded by the need for a larger number of CMOS output pins to support the same ADC resolution. 

LVDS and CML drivers do not suffer from these same limitations.  CML offers the advantage of requiring less number of output pairs per a given resolution than LVDS and CMOS drivers due to the serialization of the data.  The CML drivers specified for the JESD204B interface have an additional advantage since the specification calls for reduced peak to peak voltage levels as the sample rate increases and pushes up the output line rate.

Figure 2. CMOS, LVDS, and CML Power Consumption Comparison

Next: LVDS and CML

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