A novel partitioning strategy for analog routes for hierarchical designs
The partitioning approach has its advantages with respect to reduced die size, improved chip timing and reduced routing congestion among many. But it also has its sets of issues when it comes to physical closure. Some of the common issues are listed below.
- Inaccuracies in Synchronization between partition LEF and SOC - The routes change on top (SOC) numerous times during the design cycle. This may be because of the following reasons:
- Signal Routing congestion
- Change in analog routing requirements
- Change in Power Grid to meet IR challenges.
Re-partitioning every time with analog routing changes is time consuming and can lead to inaccuracies, which can only be caught during physical verification cycle (LVS shorts/DRC spacing), which is too late.
Figure 3. Shorts created between signals on top and metal overhangs in partitions
2 INCORRECT LEF MODELING - If USE POWER/GND is not proper in analog blocks LEF’s, partition LEF out is not modeled correctly.
Figure 4. Inaccuracies due to improper PWR/GND LEF modeling
To avoid such inaccuracies in the physical verification phase, we suggest a partitioning approach where an overlay cell is placed over the partition with blockages modeled in it, which extends beyond the actual area of the partition on all sides (metal blockages modeled in a cell).
This method benefits us in the following ways:
1) No late surprises in physical verification – This helps us prevent shorts between signals on top and routes/overhang routes inside the partition.
2) Safety Requirements Met - Since there no routing near 8um of block boundary, it takes care of the extra safety requirements that come into picture with Auto MCU’s.
3) Saving Cycle Time and Efforts - If due to incorrect USE POWER/GND definition in analog block LEF, partition LEF dumped is incorrect, correct blockages will be taken care in the overlay cell dumped. No extra time and effort spent on debugging issues that might have been earlier created by shorts.
Figure 5. Blockages modeled around the actual area of the partition
Even though the partitioning approach has many benefits when it comes to die size reduction, timing closure, and dealing with routing congestion issues; it still leads to issues in terms of physical closure especially when there are analog blocks inside the partition. The suggested partitioning strategy of placing an overlay cell over the entire partition takes care of these physical inaccuracies and helps save time and effort on debugging such issues very late in the design cycle.
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