Op amp DC error characteristics and the effect on high-precision applications

Srudeep Patil, Member of Technical Staff, Maxim Integrated -January 01, 2014

Depending on the level of precision needed in the application, we must make some careful choices for both passive component values and the op amp itself. This will be the best way to nullify the effect of input bias current on output accuracy. Therefore, selecting RP = RF//RG yields:


VOUT = - (1 + RF/RG) x (RF//RG) x IOS …..                              (Eq. 4)

Selecting RP = RF//RG helps us reduce the output error in order of magnitude. But for high-precision applications where sensor interfaces are made with large gain (> 100V/V), it is still preferable to select low-input-offset-current op amps. Also, it is not always feasible to add RP. Finally, both input bias currents and resistance sizing play important roles in output error. For these situations designers should select op amps with low input-bias current, low input-offset voltage, a low speed-to-power ratio, and high CMRR and PSRR.


Output error can be further reduced by choosing lower RF and RG which, in turn, increase the circuit’s power dissipation. A careful trade-off between output error and power dissipation needs to be maintained when choosing the size of resistances.


We return now to Figure 2B. Voltages on both positive and negative inputs produce:

VIN+ = VIN- = -RP × IBP                                                                        (Eq. 5)

Where VIN+ is the voltage at the noninverting input, and VIN- is the voltage at the inverting input.

Applying Kirchhoff’s current law on inverting input yields:

VIN-/RG + IBN -IC = 0…..                                                                     (Eq. 6)


We eliminate VIN- in Equation 6 by substituting Equation 5, which yields Equation 7 for input bias currents and current through a feedback capacitor:

IC = (RG x IBN - RP x IBP)/RG …..                                                        (Eq. 7)

Now apply Michael Faraday’s capacitance law:

VC = 1/CC  dt                                                                     (Eq. 8)

Where VC is voltage across the capacitor, which is also VOUT. Substituting Equation 7 into Equation 8 yields:

VOUT = 1/(RG x C) x Integral(RG x IBN - RP x IBP)dt…..                      (Eq. 9)

Equation 9 provides the output voltage error in Figure 2B. To minimize this error, one can select RP = RG, and that reduces Equation 9 to:

VOUT = -1/(C) x Integral(IOS) dt …..                                        (Eq. 10)

Since C and IOS are relatively constant, integrating Equation 10 over time would yield:  

VOUT = -IOS x t/C …….                                                                       (Eq. 11)   

Equation 11 implies a voltage ramp that drives the op amp into saturation.



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