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Novel method detects lock in Costas loops

-June 22, 2000

In the well-established lock-detection scheme for conventional PLLs, the VCO or VCXO local oscillator splits the output into 0 and 90° signals (Figure 1). The incoming IF signal mixes with the 0 and 90° signals to perform phase locking and lock detection, respectively. This method gives unambiguous results even under noisy conditions.

For Costas-loop systems for binary-phase-shift-keying demodulation, the demodulation process uses both the 0 and the 90° signals. Thus, these signals are unusable for lock detection. Instead, simple Costas-loop systems generally use level detection as the lock-detection method (Figure 2a). This straightforward method involves detecting and comparing the demodulated I and Q signal levels. In the locked condition, the I-data level is more than the Q-data level. In this condition, the Q-data level equals 0. In the unlocked condition, the two data levels are equal. The scheme detects this difference to indicate lock. Unfortunately, this method can give ambiguous results under noisy conditions.

You can adopt a similar method in modified Costas loops for QPSK (quadrature-phase-shift-keying) demodulation (Figure 2b). In the unlocked condition, a beat-frequency component is present along with the data. In the lock condition, this beat-frequency component disappears. Hence, the detected I and Q data levels are higher in the unlocked condition than in the locked condition. By detecting this difference in levels, you can determine the locked condition. This method is not free of ambiguities under noisy conditions because the detected levels change with levels of noise. Thus, reference-voltage settings for level comparison are critical. At some levels of noise, level comparison becomes almost impossible; under such conditions, this method of lock detection fails.

The coherent method illustrated in Figure 2c gives ambiguity-free lock detection for modified Costas-loop systems. Unfortunately, this method is complex, and the hardware realization is as complex as the demodulation process itself.

Figure 3 presents a new method of lock detection with much less hardware complexity. You can adopt this level of detection for any PLL system. The underlying principle of this method is that when the PLL is in lock, it tracks and neutralizes all of the low-frequency modulations within the loop. Therefore, if the system introduces a low-frequency, low-level modulation, such as at the loop-filter input, into the loop, then when the loop is locked, the low-frequency signal at the output of loop filter disappears. The presence or absence of the signal at the output of the filter provides unambiguous lock detection.

The circuit in Figure 3 implements this method in a 375-MHz QPSK demodulator with a loop bandwidth of 10 kHz. This method involves injecting a low-level, 50-Hz sine wave at the input of the loop filter, which is an active filter, and injecting a sweep signal of 2 Hz, which speeds lock acquisition. If you use a passive filter in place of the active filter, you can apply the signal at the input of VCXO after the loop filter, that is at the input of the amplifier after the passive loop filter.

The scheme taps the output of the loop filter and filters out the sweep signal. The scheme then amplifies the 50-Hz signal to compensate for attenuation in the loop filter and rectifies the signal to give a dc voltage to indicate its presence. When the loop is in lock, the 50-Hz signal disappears, and the rectifier output is zero. The lock-indication output also cuts off the sweep. The 50-Hz signal remains connected to the loop filter even during lock. The presence of this signal at the input of the loop filter does not degrade the demodulator performance because the level is low. You choose 50 Hz as the injected signal frequency because 50 Hz is considerably higher than the sweep-signal frequency and considerably lower than the loop bandwidth.

The performance of this method is effective even under very noisy conditions, such as when the input's Eb/No (energy-per-bit-to-noise) figure is 3 dB. Previous methods give ambiguity-free results only at Eb/No levels of 7 or 8 dB. (DI #2545)


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