Growing audio requirements in SoCs

Henk Hamoen, Senior Product Marketing Manager, Synopsys, Inc. -August 07, 2012

As consumer devices such as tablets, media players and home theater systems continue to incorporate more audio functionality, the systems on chip (SoCs) designed for these devices become more complex. These SoCs must support a growing list of audio requirements such as a wider range of high-definition audio compression formats, multi-channel audio content, higher sampling rates and advanced audio post-processing functions.

In addition to the DSP audio processor, audio SoCs need seamlessly integrated analog codecs to provide connections for microphone, line, headphone and speakers, as well as digital peripherals (e.g. I2S, S/PDIF). To deliver the necessary features, designers need to integrate more IP into the SoCs, and they need to do it with fewer resources, smaller budgets, and shorter project schedules.

Figure 1: The increasing complexity of audio feature requirements

Innovations in IP integration have traditionally been focused on the hardware aspects, but what really drives system complexity is the software. For audio applications, the software stack needs to support the latest audio standards from companies such as Dolby Laboratories, SRS Labs, DTS and Microsoft, as well as open source formats like Ogg/Vorbis and FLAC. All of these software components must be integrated in a media streaming framework and then into the application software running on the host processor.

Project schedules, which ultimately drive the dates of when the product is introduced to the market, are largely determined by the time it takes to build the entire application software stack. The ability to quickly integrate all the necessary hardware and software IP into a complete system can turn a great design undertaking into a real business success. Being the first to market with the right features at a lower cost is a significant differentiator.

Design teams that leverage a pre-verified hardware and software IP subsystem can drastically reduce design integration effort, lower integration risk and accelerate time to market. IP subsystems enable them to take advantage of higher integration levels and the latest technologies for system integration, including prototyping to accelerate software development and full system validation.

What is a Complete, Pre-integrated and Pre-verified Audio IP Subsystem?
Most IP suppliers today only provide the individual hardware components and some pieces of the software (for example, just the audio processor and a set of individual software codecs and simulation models). Integrating all of the IP and creating the full software stack is left to the SoC integrator, who needs to carefully configure and connect all of the IP together; a tedious and time-consuming effort.

Often, both hardware and software portions are missing and have to be added by the design teams in order to create the complete 'end-to-end' solution. A complete audio subsystem includes an audio processor that is optimized for high-definition voice and multi-channel surround sound; analog (line in/out, speaker and microphone) and digital (I2S and S/PDIF) interfaces; infrastructure components including clock management; and a significant amount of audio software.

Audio Processor – At the Heart of the Subsystem
Audio processors are really optimized for … processing audio data! There have always been many different audio formats, with the most popular one today being MP3. New formats are being introduced every day, probably even now as you read this article. This will only continue and is largely driven by demands in the end-user (consumer) market.

With devices being connected to the internet, either via WiFi or 3G/4G networks, typical mobile formats are now appearing in home devices and vice versa. A great example is having multi-channel, high-definition audio on a semi-portable device like a tablet; that in itself only has a stereo analog (headphone) output yet can playback audio to a home cinema system with surround speakers through an HDMI (High-Definition Multimedia Interface) or WiFi connection.

Audio processors therefore need to be prepared for high-definition formats, which is where a 32-bit processor is ideal. Technologies in the market include processors that are based on very long instruction word (VLIW) architecture, whereas modern RISC-based processors with DSP extensions are more efficient in terms of silicon area, processing capacity and power consumption. All the parameters (for example cache sizes) inside the processor should be configurable by the designer because they know best how the target system behaves and how the processor fits in best.

Audio data is stored in system memory, (e.g. double data rate (DDR) memory), a shared resource in the system. For applications that also require a lot of video or graphics processing such as set-top-boxes and other media intensive devices, multiple processors need to share the same system memory, which results in an increase in memory access latency.

Just a few years ago these latencies were on the order of 50 to 100 cycles, but today we see these going up to 200 or even 400 cycles. This latency impacts the performance of any processor, although some more than others. A straight-forward method to compensate for this is the use of prefetchers. Prefetchers read data from memory and anticipate their need on their previous access, which often leads to mis-predictions.

Another method is the use of an "XY memory," which allows concurrent fetching and processing of much larger data blocks. While data 'X0Y0' is being processed, the next block 'X1Y1' is already being transferred from memory. And, since the processor knows exactly where in memory the data is, the efficiency is much higher than that of a processor that uses prefetchers.

As a result, audio processors with an "XY memory" architecture are much more tolerant to system memory latencies than processors using prefetchers. For the same increase in system memory latency, the processor with an XY memory will require fewer extra processing cycles, resulting in a lower clock frequency or more spare capacity.

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