Digital I/O in chunks: distribute control and status

Jon Gabay, Dr. Gizmology -September 17, 2012

Jon Gabay, aka Dr. Gizmology, continues his do-it-yourself series. Last month, this series showed how to use an IIC-to-parallel bus converter chip (the PCF8574) to completely connect and drive a parallel LCD character display module using only four wires. We were able to eliminate 12 wires of the normally used 16 wire connector to drive the display from our host microcontroller, and drive more than one display.

Typically, a machine or project that uses a small character display also uses pushbuttons and switches as well as status LEDs as part of a user interface.

But here again, a simple four button array will use five wires (one common, four unique). Similarly, a bank of eight status LEDs will add another nine wires. We’ve just added 14 wires for two simple user interface panel pieces. If we need a tamper switch, beeper, an open case detector, or other front panel functions, we are looking at a huge bundle of wires and connectors. This increases cost, complexity, and can reduce reliability.

We mentioned previously that the PCF8574 chip features a state change detection capability. This means it will generate an interrupt for us when state change occurs. The alternative approach would be to have our processor polling constantly to look for a button press.

This month, we are going to take advantage of that feature and use it to create a series of small and modular user interface blocks that can connect to the same IIC bus. In this case though, we are going to add a wire for the real time interrupt. We will add a spare, as well. You never know when this can save the day.

Quasi bidirectional functionality

The eight port pins on the 8574’s parallel side (P0-P7) have latched outputs with high current drive capability designed for driving LEDs. They use a quasi bidirectional structure that allows input or output to take place without the use of an active data directions signal typically used with most bidirectional drivers (Figure 1).

When powering up, the I/O is high, but without strong pull up resistors until the output is written to. The strong pull up is turned off by the negative edge of the IIC clock. A logic 1 is written to any I/O pin you want to use as an input before you read it. When used as inputs, the weak logic 1 (100 uA) is easily pulled low by the output feeding the pin.

Another thing to note is that the interrupt pin (INT) is open drain. That means a pull up somewhere is required. It also means that a common interrupt line can share interrupts from several of these devices and then determine the interrupting source.

Any rising or falling edge on any input pin can generate an active low interrupt. When data on the port is read or changed, the interrupt is deactivated.

Simple software

One nice thing about the PCF8574 is that the data structure is very simple (Figure 2). When first writing to it, byte number 1 holds the address which consists of the chip address (0100xxxx), and the locally strapped address using the external A0-A2 (xxxx, A2, A1, A0, x) pins. The least significant bit of the first byte transferred tells the chip whether or not this is a write operation (0) or a read is to take place (1).

The next byte clocked is the data; out to the 8574 if it is a write operation, or in from the 8574 if it is a read operation. But that’s not all. You can eliminate the first address byte after the first cycle by streaming data byte after byte (Figure 3).

This is useful for generating test patterns or sequential values like address counters, Bi-Phase encoded signals, or even analog waveforms through an R/2R ladder. This can also be ideal to control stepper motors while monitoring limit switches.

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