Simple FIFO provides data-width conversion
Many designs require FIFO elastic buffers to form a bridge between subsystems with different clock rates and access requirements. However, in some applications, you need FIFO buffers for data conversion. One example is the case in which you need to connect an 8-bit ADC to a 16-bit data-bus microprocessor through a FIFO buffer (Figure 1). Unfortunately, most currently available FIFO buffers are unsuitable for this application. This Design Idea describes how to implement a common clock (synchronous version) for an FPGA-based FIFO for data-width conversion with different-width read and write data ports. You can implement this FIFO using a Xilinx (www.xilinx.com) Spartan II Series FPGA. The method uses an on-chip DLL (delay-locked-loop) macro, distributed memories, and simple counter logic (Figure 2).
The width of the input data of the FIFO is 8 bits; however, the width of the output data is 16 bits. You use only one common clock for both read and write actions. The trick is to use a clocked DLL, which not only minimizes clock skews, but also offers a double-frequency output clock. So, you can implement a double data rate for the input data, write_data_in. By monitoring a sample of the DLL output clock, the DLL can compensate for the delay on the routing network, efficiently eliminating the delay from the external input port to the individual clock loads within the device. Instead of using block memory, this design employs distributed memory to hold the data in FIFO. In fact, choosing block memory or distributed memory depends on how important this FIFO is in your system. If it is not critical, you may want to consider using distributed memory.
You can put the memory anywhere you like within the FPGA. If you insist on using block memory, you can easily modify the VHDL code. You can just use some RAM macros to replace distributed memories. Click here to download the VHDL code for the FIFO. FIFOs commonly use Gray-code counters or linear-feedback shift registers as read or write counters. To minimize the logic size, this design uses only two integers ranging from 0 to 7 together with a carry for the counters. When the read and write counters are equal and the carry is zero, the FIFO is empty. When the write counter plus one is equal to the read counter and the carry is one, the FIFO is full.
Is this the best Design Idea in this issue? Select at www.edn.com.