More-than-Moore memory grows up

-December 09, 2012

This article is part of EDN's Hot Technologies: Looking ahead to 2013 feature, where EDN editors and guest contributors examine some of the hot trends and technologies in 2012 that promise to shape technology news in 2013 and beyond.

Moore’s Law may not be running out of steam, but it may be running out of money, as scaling to smaller geometries becomes more cost prohibitive. We also have an insatiable appetite for memory these days, but our tastes are changing from DRAM to nonvolatile memory—a market largely served by flash devices. Whereas DRAM can possibly scale down to 1 nm, we are already encountering floating-gate scaling problems for NAND flash. The answer to the scaling problem appears to be growing devices “up”; the question is how best to do it.

Three-dimensional die stacking uses a silicon interposer and TSVs (through-silicon vias) to connect the stacked dice electrically, allowing the integration of multiple, smaller dice—each processed using an optimal technology—within a package. Many memory manufacturers are already creating 3-D die-stacked chips in production quantities (Figure 1), and the technology’s use for memories paves the way for its use elsewhere.

Figure 1 Use of 3-D stacking in memories such as this Micron hybrid memory cube opens the door to the
technique’s use for other ICs.

Indeed, we are already seeing the first general market utilization in FPGAs, using a slightly simpler construction; the silicon interposer contains routing only and no active logic (Figure 2). This technology is likely to become mainstream within the next five years for stacking memory on top of processors.

Figure 2 Die stacking in FPGAs uses a slightly simpler construction wherein the silicon
interposer contains routing only and no active logic.

Toshiba is pushing 3-D NAND processes with its p-BiCS (pipe-shaped bit-cost scalable) technology. Rather than stack multiple substrates and connect them using TSVs, the approach builds cells on top of each other to create U-shaped bit lines. Toshiba says the process becomes cheaper than traditional NAND processes when more than 15 layers are created.

Macronix is poised to unveil working 3-D NAND flash memory at sub-40 nm. The new architecture enables the use of a “staircase” bit-line contact formation method (Figure 3). The result is an eight-layer device with a wordline feature size of 37.5 nm, bit-line feature size of 75 nm, 64 cells per string, and a core array efficiency of 63%. The researchers say the technology not only is lower cost than conventional, 2-D sub-20-nm NAND but also can provide 1 Tbit of memory if further scaled to 25-nm feature sizes. At that size, the Macronix device would comprise only 32 layers, whereas 3-D stackable NANDs with vertical channels would need almost 100 layers to reach the same memory density.

Figure 3 A staircase construction accesses layers in a vertical stack of cells.

Also watching:

Some propose forgetting electrons and going back to magnetic memory, but what’s the best way to program them? Two ideas:

  • Form memory cells from two ferromagnetic plates, each of which can hold a magnetic field, separated by a thin insulating layer (Figure 4).

Figure 4 An MRAM cell can be created using a fixed magnet.
  • Create spin in electrons using magnetic fields.

Read more of EDN's Hot Technologies: Looking ahead to 2013:

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