Design planning for large SoC implementation at 40nm - Part 2

-July 12, 2013

[Part 1 discusses exploring the process technology to learn its capabilities and limitations, including evaluating the technology libraries, determining the implementation tools and flows, and capturing the SoC requirements.]

Die-Size Estimation
Die size and power estimations are at the foundation of SoC implementation. The key is how early and how accurately can it be done. These two parameters are the main data point for making some critical decisions early on. Freezing the die size in the early phase of SoC development gives a solid foundation for the physical designer, but it is a challenge to come up with an optimum and realistic estimation.

The top-level physical designer should engage with the RTL designer early on in terms of assessing the growth of the blocks and then binding them into the floorplan. The physical designer should come up with an early floorplan and continue to refine it for optimum and realistic die size. Memories significantly impact the die size, hence the front-end engineer should try to close on number of memory requirements early on. It is wise to keep a margin for the growth of the blocks.

Additional routing requirements due to DFT must be accounted for. It's very important to engage with the top-level DFT architect while estimating the die size. The routing requirement can vary significantly based on the Scan and BIST architecture. For example, if the compressor is sitting within a block, then the routing requirements at the top level will be less; and if the compressor is sitting outside the block, then the compressor grouping and placement will determine the congestion within the vertical and horizontal channels. Similarly the BIST controller within each block, and its communication with the top-level server, will also be important to understand while estimating the die size.

Die-size estimation and early physical architecture must go hand-in-hand. For channel based hierarchical designs, appropriate estimation of vertical and horizontal channel widths is important. While estimating the channel requirements, it is important that the physical designer considers all the crucial factors, such as the routing requirements for critical clocks, critical signal routing, additional routs due to DFT and MBIST and space margins for addressing crosstalk. A designer should understand the metal stack and decide how to allocate the routing resources.

Another aspect that cannot be ignored is the packaging requirement. For example the ball out and the bump plan can have a significant impact on die size. There could be a business decision for a certain kind of package and package design, which might drive the die size. There could be a legacy ball map, which might impact the placement of some physical IP or block and therefore affect the floor plan. So it is important to look into this early on. It's better if the bump plan can be made near final before finalizing the die size. Package design and die design must go hand-in-hand.

It's paramount to engage with packaging while estimating the die size. A continuous methodical and data driven interaction between the physical designer and package engineer is a must. There are many key parameters that package engineers validate and simulate prior to determining the package requirement, which depend upon data from physical designers.

Some of the factors related to design are die size, pad ring design, special IO constraints, interconnect technology (types of flip-chip, wire bond) and voltage domains. Additionally, there are other package-related analyses such as mechanical performance, electrical performance, thermal performance, reliability and most important the cost.

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