BIST grouping optimization for large-scale embedded memory design

, & -August 30, 2013

Design-for-test (DFT) engineers often struggle to develop a memory built-in self-test (BIST) grouping plan, deciding which memories belong to which BIST group, to improve test time, routing effort, and minimize area overhead. Memory BIST grouping is so complicated that the grouping process requires a significant amount of design time and can prove unreliable if the amount of memory is large. In order to facilitate the process, an automation tool and convenient interface is required to speed the process and guarantee grouping quality.

It currently takes DFT engineers several hours to group memories for BIST on a design that features hundreds of memories. Figure 1 shows that, as the number of memories increases, the time spent on BIST grouping increases exponentially. For a design with thousands of memories, when all tasks are taken into account--grouping constraint, test time, routing effort, and area overheadit is exceedingly difficult to achieve reliable memory BIST grouping results in a compressed amount of time.

time spent on BIST grouping
Figure 1 As the number of memories increases, the time spent on BIST grouping increases exponentially.

Figure 2 shows the flow for BIST group adjustment that reduces the amount of routing effort. BIST grouping depends upon the floor plan of the net list, taking into consideration memory locations. The flow is executed iteratively each time the net list or floor plan is updated. When the number of memories or the floor plan is changed, the BIST memory group must also be adjusted to shorten test time and minimize routing resources.

design flow for memory BIST group adjustment
Figure 2 Here is the design flow for memory BIST group adjustment.

Without the tool’s help, designers will be iteratively defining BIST groupings significantly extending design time.

Constraints on BIST memory grouping

There are always both "hard" and "soft" constraints that come into play when grouping memories for BIST.

Hard constraints preclude organizing memories of different constraint types into the same BIST group. Hard constraints include: power domains, frequency domains, synchronous/asynchronous memory types, and user-specified constraint. Memories in different power and frequency domains cannot be grouped in the same BIST, and synchronous memories cannot be grouped with asynchronous memories in the same BIST either.

Soft constraints limit the final grouping result to a specified target but do not necessarily restrict BIST members when taking into consideration parameters such as area overhead, test time, power, and routing efforts. In some cases, DFT engineers attempt to reduce area overhead by restricting the number of BIST to a maximum value. Alternatively, restriction on test time prevents long test run times. To prevent an IR drop problem, power is a consideration during memory BIST testing. Critically, routing must be reduced.

All constraints should be considered when assembling BIST grouping. But for soft constraint in particular, there is the inevitable trade-off between test time, power, and area overhead. Assuming that all BISTs are tested in serial and memories are tested in parallel, to reduce area overhead on the BIST circuit the number of memories in a BIST must be increased. That, in turn, leads to an increase in power consumption. If BISTs are tested in parallel and memories are tested in serial, the decreased BIST number will result in increased test time. Conversely, reducing test time will impact area overhead or power.

Smart memory BIST grouping

Smart memory BIST grouping allows DFT engineers to use an algorithm to automatically group memories or to manually group memories through the GUI interface. The best results have been achieved so far by using automatic grouping and then adjusting BIST groups based on a customized design spec for what-if analysis (Figure 3).

Smart memory BIST grouping
Figure 3 Smart memory BIST grouping in use.

To run memory BIST grouping on SMBG, prepare the memory floor plan (DEF), memory information (LEF), power domain information, and the request form. The request form is a file to record the BIST grouping result, ungrouped memories, and other information. The project environment can be recorded into a SMBG script and read from SMBG (Figure 4). Engineers can also specify their own constraints for the project in the SMBG script.

SMBG script
Figure 4 The project environment can be recorded into a SMBG script and read from SMBG.
Click image to enlarge

SMBG integrates an automatic grouping algorithm and GUI interfaces to allow manual tuning. An automatic grouping algorithm provides an initial grouping result based on the floor plan. Engineers can then adjust the grouping result for what-if analysis.

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