DPGA conditions signals with negative time constant

-March 19, 2009

DPGAs (digitally programmable-gain amplifiers) amplify or attenuate analog signals, which maximizes an ADC’s dynamic range. Most monolithic DPGAs, such as the Linear Technology LTC6910 and the National Semiconductor LPM8100, use a multiplying DAC in an op amp’s feedback loop so that the DAC’s input code sets the amplifier’s closed-loop gain. Instead of using a monolithic DPGA, you can use two op amps and three analog switches to build a DPGA employing negative time constants.

You’re no doubt familiar with the e–t/RC convergent exponential in which a capacitor in an RC circuit asymptotically discharges to zero. For input voltage, V=VIN/2 at t=T=loge(2)RC, V=VIN/4 at t=2T, V=VIN/8 at t=3T, and so forth. Less familiar, but just as simple, is the behavior of the same RC topology when you replace R with an active circuit that synthesizes a negative resistance (Figure 1). If you replace resistor R with –R, you create a positive RC time constant. Thus, you create a divergent exponential, VINe+t/RC.

Instead of converging to zero, the waveform theoretically diverges to infinity, and V=2VIN when t=T, V=4VIN at t=2T, V=8VIN at t=3T, and so forth. Therefore, you can amplify the input voltage by simply waiting the right amount of time (t=log2(V/VIN)T) after starting the negative discharge. The divergent exponential and the negative time constant are the core concepts of the circuit in Figure 2.

See all of EDN's
Design Ideas

You can program the amplifier’s gain with a PWM (pulse-width-modulation) signal from a microcontroller or another circuit. When the PWM signal goes to logic zero, sample-and-hold capacitor C1 charges to VIN. When the PWM signal cycles to logic one, op amp A1 drives the R1C1 positive-feedback loop, creating a negative time constant. The resulting divergent exponential rise of C1’s charge continues as long as the PWM signal remains at logic one. That situation creates a net voltage gain of:

VOUT(t)=VIN2(t/10 μsec+0.5).

Thus, gain=2(t/10 μsec+0.5) and log(gain)=3+0.6 dB/μsec. At the end of the amplification cycle, when PWM returns to logic zero, amplifier A2 captures and holds the amplified input voltage.

The logarithmic relationship between gain and timing provides excellent gain resolution even when a PWM signal has just 8 bits of resolution and its programmable gain has a range greater than 0.2 dB/LSB step. (Click here to view the log and linear plots of gain versus time using the amplify phase.)

The accuracy and repeatability of the timing of the exponential signal, the ADC sampling, the jitter, and the RC-time-constant stability all limit the amplifier’s gain-programming accuracy. In Figure 2, 1 nsec of timing error, or jitter, produces 0.007% of gain-programming error. Fortunately, the near-ubiquity of programmable-timer/counter hardware in microcontrollers and data-acquisition systems usually makes it easy to digitally generate a highly repeatable PWM-control signal.

Loading comments...

Write a Comment

To comment please Log In