EDN Access--12.04.97 DDS forms inphase and quadrature generator

-December 04, 1997

December 4, 1997

DDS forms inphase and quadrature generator

J Toda, R Bragos, and M Tresanchez, UPC, Barcelona, Spain

Many instrumentation applications use two sine waves to carry out coherent modulation. The circuit in Figure 1 allows you to measure vector magnitudes (for example, voltage or impedance) by multiplying the measured signal with inphase and quadrature sinusoidal signals of the same frequency. In a classic approach, these signals come from one VCO and a pi/2 (90º) delay. However, when the measurements cover a wide frequency span, it is necessary to compensate phase differences between the measured and instrument circuits by using a programmable delay. The problem is that a programmable-delay circuit usable across large frequency spans (for example, seven decades) is difficult to implement.

This circuit solves the problem by using two chips. The circuit takes little board space and provides precise phase matching. Direct digital synthesis (DDS) allows you to generate periodic signals using a numerically controlled oscillator (NCO) and a DAC. The NCOs' look-up table stores a set of sinusoidal values. Reading these values in appropriate order, the system generates a sinusoidal signal. A phase register changes the table-reading speed and produces different frequencies without affecting the sampling rate. You can also program the DAC to produce different amplitudes.

A DDS system is suitable for generating sine waves over large frequency spans, with programmable phase delay and amplitude if desired. Also, some DDS chips (for example, the AD7008) include the DAC output. This inclusion is convenient in instrumentation applications, because it reduces the number of noisy, high-frequency digital lines. However, this IC has two analog outputs with a fixed 180º phase shift between them. Thus, to generate the quadrature signals, you need two DDS systems. However, a new problem arises: the lack of a synchronization mechanism for a set of AD7008s. The chip's sleep line stops the NCO's internal clock, but this utility is inadequate to synchronize the phases of the two DDS systems.

The circuit of Figure 1 uses a passive synchronization system based on simultaneous data load. The circuit uses the serial port of the DDS chip; you could also use the faster parallel port. The method shares all the lines used for programming the DDS ICs except the data lines. You can thus simultaneously program the two AD7008s with different data; that is, with a different phase delay for each chip. The only restriction is that you must route the critical timing lines (reset, clock, and load) in such a way that the line lengths from the signal source (the 50 ohm clock) to the signal sink (the two chips' clock inputs) are equal.

Also, note that the µC's timing signal (reset) must be synchronous with the clock signal of the DDS chips. Figure 2 shows the phase error between the inphase and quadrature signals. The error is less than 0.1º for frequencies as high as 100 kHz, less than 0.5º to 1 MHz, and less than 1.5º at 10 MHz. The vertical lines show the standard deviation for each measurement. (DI #2126)

Figure 1
Two DDS chips allow you to generate inphase and quadrature sinusoidal signals over a wide frequency range with low phase error.
Figure 2
The circuit in Figure 1 yields phase errors of less than 18 over most of its operating-frequency range.

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Copyright c 1997 EDN Magazine, EDN Access . EDN is a registered trademark of Reed Properties Inc, used under license. EDN is published by Cahners Publishing Company , a unit of Reed Elsevier Inc.


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