EDN Access--12.05.96 Frequency divider adapts to I/O condition

-December 05, 1996

EDN logoDesign IdeasDecember 5, 1996

Frequency divider adapts to I/O conditions

Edited by Bill Travis & Anne Watson Swager  

Steve Hranilovic, University of Waterloo, Waterloo, ON, CanadaThe circuit in Figure 1 accepts an input clock signal, such as from a crystal oscillator, and divides the frequency according to the input divisor word. You can easily modify the basic design of this versatile PLD-based divider to handle different I/O conditions. The design uses the FLEX8000 family of PLDs from Altera Corp (San Jose, CA).

The core of the design generates the appropriate edges to toggle the output T flip-flop to create a clock signal with a duty cycle of approximately 50%. The input divisor word serves as the reference for the 8COUNT countdown counter. This counter counts down from the divisor word and raises the COUT flag when the count reaches zero. The complement of COUT synchronously resets the reference value of the counter to restart the process.

A comparator generates the second edge necessary for the correct output. The circuit divides the input word by 2 (using "right bit shift one bit") and compares the result to the state of the 8COUNT counter. When the two values are equal, the comparator output is high for one clock period of the input frequency. D flip-flops latch the pulses from the countdown flag and from the comparator using clock signals with the correct phasing of the input frequency to produce a 50% duty cycle.

ORing the signals together produces a series of pulses. Each pulse is one period of the input frequency, and the rising edges of the pulses occur at the correct locations to toggle the T flip-flop at the output. A value of N for the input word produces an output frequency N+1 times smaller than the input frequency because there are N+1 transitions.

Simulations show that when N is even, which results in division by an odd number of N+1, the output clock has a 50% duty cycle. N's being odd results in division by an even number, and the high time of the output clock is longer than the low time by one period of the input clock. This discrepancy has a drastic effect on duty cycle at small value of even N, but the impact diminishes as N increases. This feature has no bearing on the frequency of the output, which is always correct.

The circuit in Figure 1 also depends on an input clock signal that has a 50% duty cycle. When the input is not 50%, you can modify the design to use only the positive edge of the input signal to generate the divided-down output. You can use the same countdown counter and comparator as in Figure 1. However, you need to latch the output after the OR gate, which delays the zero flag by one input clock. Although this design requires no 50%-duty-cycle input, it still results in a not-quite-50% duty cycle for even values of N.

For systems that are sensitive to duty cycle, you can further modify the circuit (Figure 2). This version also uses the countdown counter and comparator but changes the value of the comparator's reference. In this circuit, an adder computes the reference value of N/2. The circuit then latches the zero-flag and comparator pulses on the appropriate edges of the input clock to produce a 50% duty cycle. The output duty cycle is nearly 50% for both even and odd values of N. As with the circuit in Figure 1, this circuit also relies on an input with a 50% duty cycle. (DI #1956)

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